EPE Association: EPE 2025 - DS1k: Active Devices and Components

EPE 2025 - DS1k: Active Devices and Components
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2025 - Conference > EPE 2025 - Topic 07: Semiconductor Devices and Packaging > EPE 2025 - DS1k: Active Devices and Components

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   Characterization of an Integrated GaN Driver for Power Switching Applications
By Benedikt KOHLHEPP, Houssam HALHOUL, Nick WIECZOREK, Xiaomeng GENG, Lars SCHELLHASE, Oliver HILT, Sibylle DIECKERHOFF [View]
[Download]

Abstract: Modern GaN-HEMTs require appropriate driving circuits to enable fast switching. Thus, monolithic integration of power switches and gate drivers is necessary. Therefore, this paper demonstrates a GaN driver to control a GaN power switch. Besides static and pulsed characterization, the driver's performance is validated through continuous switching tests, demonstrating effective operation with turn-on and turn-off times of an emulated load of 1.68 ns and 1.84 ns, respectively.

   High temperature characterizations of a monolithic 900 V GaN power device for current source inverter applications
By Van-Sang NGUYEN, René ESCOFFIER, Stephane CATELLANI, Anthony BIER [View]
[Download]

Abstract: Based on the recent works [1-4] on the current source inverter for photovoltaic (PV) application with Silicon Carbide (SiC) devices, this work presents the design and the characterizations of a monolithic GaN (Gallium Nitride) device where the GaN transistor and the diode in series connection are built up on a single chip for a specific current source inverter topology. This work presents the details of this monolithic 900 V GaN device in the first section, and then the static characterizations by using of an automatic industrial equipment (B1506 from Keysight) with a high temperature thermostream will be shown in the second section. A specific double pulse test-bench is detailed for high temperature dynamic characterization with the high speed current and voltage probes, this monolithic GaN device can be heated-up locally up to 175°C by using an infrared beam station.

   Losses Evaluation on Parallel Diodes Using a Double Pulse Test Circuit
By Gustavo HENN, Frédéric RAYMOND-LARUINA, Herminio DE OLIVEIRA FILHO, Tanguy PHULPIN [View]
[Download]

Abstract: This paper aims to optimize efficiency by combining diodes, such as SiC Schottky or PiN Si in parallel. For each combination, conduction and switching losses are estimated using datasheet in addition to double pulse test circuit validation. The parallelization of each diode is studied to propose the best configuration.

   Maximize advantages in hard and soft-switching applications with optimal use of a modern SiC MOSFET with low output capacitance
By Jaeeul YEON, Syeda Qurat ul ain AKBAR, Qibin WU [View]
[Download]

Abstract: Silicon carbide (SiC) MOSFETs have superior properties at high voltage and high power compared to silicon (Si) devices in almost all aspects due to their material advantages such as three times larger band gap, three times larger thermal conductivity, ten times higher critical electric field, two times higher saturation velocity and so on. SiC MOSFETs can thus significantly improve the performance of the system. In addition to the well-known advantages of SiC MOSFETs over Si MOSFETs and IGBTs, a deeper understanding and right usage of SiC MOSFETs can help enhance device performance and maximize system value propositions. In this paper, a parameters-oriented approach is proposed to select the right SiC MOSFET device corresponding to the requirements of each application. The proposed approach has been validated by PLECS simulation results of representative hard and soft switching applications.

   Measurement Techniques of Threshold Voltage Shift and Recovery in GaN e-HEMTs
By Burhan ETOZ, Arkadeep DEB, Jose ORTIZ-GONZALEZ, Layi ALATISE [View]
[Download]

Abstract: This paper presents two different techniques of threshold voltage shift (_VTH) and recovery characterisation in GaN e-HEMTs. The first technique applies a stressing gate voltage (VGS) of defined magnitude and duration and then measures a _VTH at different time intervals by shorting the gate-to-drain terminals of the e-HEMT while passing a sensing current trough the drain-source. In the second technique, after the VGS stress, a sensing current through the 3rd quadrant of the GaN e-HEMT is used to measure the 3rd quadrant voltage as an indicator of _VTH. Both measurements show the same trends. With positive VGS stress, _VTH is positive (due to electron capture at the p-GaN/AlGaN interface) and then becomes negative over time due to faster electron release than hole release. The magnitude of the initial positive _VTH is proportional to the VGS stress while the recovery rate is inversely proportional of VGS stress.

   Modelling of SiC and GaN Transistors Based on Pulsed S-Parameter Measurements
By Martin HERGT, Bernhard HAMMER, Martin SACK, Lukas W. MAYER, Sebastian NIELEBOCK, Marc HILLER [View]
[Download]

Abstract: For the design of fast-switching inverters a precise model of power semiconductors is required. Based on pulsed S-parameter measurements in the frequency range of 2 MHz to 500 MHz a SiC MOSFET and a GaN HEMT have been characterized. As basis for precise modelling, measurements under varying load conditions have been taken for many operating points covering the pinch-off, ohmic, and active regions. The employed model to describe the transistor uses a circuit comprising 12 circuit elements. Thereby, the elements of the intrinsic transistor vary with the transistor's operating point and parameters describing the influence of the package are considered to be constant. The model parameters have been adjusted iteratively. A comparison of the obtained model with the original S-parameter measurements exhibits an excellent match.

   Parasitic Capacitances Effect on Transient Current Sharing in Parallel Connection of GaN FETs
By Salvatore MUSUMECI, Vincenzo BARBA, Michele PASTORELLI, Marco PALMA [View]
[Download]

Abstract: The paper deals with the impact of parasitic capacitance on the switching operation of GaN FET devices in parallel connection. A suitable experimental board has been developed to investigate the switching transient current share features for several GaN FETs connected in parallel to perform a single high-current switch. Every device can be driven independently, and a source shunt per each GaN FET monitors the transistor current. Simulation runs and experimental tests show the switching mechanism and parameters involved in the transients' current share. The paper aims to give insights into the designing boards of paralleled GaN FETs regarding the influence of parasitic capacitances in the transient current peak distribution to find the maximum parasitic capacitance reachable without overcoming the limit of impulsive device current. The study contributes to developing reliable power modules made of several GaN FETs in parallel connection.

   SiC MOSFET turn-off overvoltage measurement
By Mikel GALDEANO, Ernesto Luis BARRIOS, David ELIZONDO-MARTINEZ, Pablo SANCHIS [View]
[Download]

Abstract: Selecting the appropriate measurement system is crucial in power electronics. This is especially important during MOSFET's turn-off process, where it is essential to measure the voltage rise and accurately capture the peak overvoltage. During turn-off, the interaction between the MOSFET and the parasitic element of the PCB creates a resonance. This phenomenon leads to an overvoltage, which peaks at the resonance frequency and can potentially damage the device. This paper discusses the characteristics of the measurement system needed to capture the peak overvoltage accurately. A step-by-step guide is proposed to ensure the correct selection of the probe and its correct use. This guide is experimentally validated on a three-level converter, where drain-source voltage measurements have been performed with and without a ground reference. The drain to source measurement method proposed in this paper is accurate, cost-effective and capable of minimizing induced noise.

   Static vs. Dynamic Characterization of p-GaN HEMTs: Discrepancies in Electrical Characteristics and their Dependence on Bias History
By Ludovic ROCHE, David TRÉMOUILLES, Emmanuel MARCAULT, Corinne ALONSO [View]
[Download]

Abstract: Quasi-static electrical characteristics of p-GaN HEMTs fluctuate with bias history. This study evidences that dynamic operation is fortunately highly reproducible without pre-conditioning. The original experimental setup highlights that quasi-static data alone is insufficient for modeling dynamic behavior, while allowing precise detection of discrepancies, enabling improved transient modeling.

   Test Setup for Measuring the Impact of Gate Stress on a GaN-HEMT's Output Characteristic
By Daniel BREIDENSTEIN, Sophia ROESEL, Benedikt KOHLHEPP, Thomas DUERBAUM [View]
[Download]

Abstract: Precisely estimating conduction losses requires knowledge of the device's output characteristic in the ohmic region. For GaN-HEMTs, it dynamically depends on time, temperature, and applied biases. To study the impact of gate bias over time, a transient measurement approach is applied, that can acquire the start of the output characteristic with a single pulse. This ensures neglectable impact of temperature changes and trapping state on the single measurement. In addition, the short acquisition time allows studying the impact of the bias in the milliseconds range. Therefore, the measurement pulses are altered with stress intervals. While reference measurements for a traditional Si-MOSFET under constant gate bias show almost no change in the output characteristic over time, test results for a commercial GaN-HEMT reveal changes for low gate voltages. This demonstrates that the user should at least be aware of such trapping problems effecting measurements, which may lead to differences in characterization and application.

   Using SiC JBS diode as voltage clamping in SSCB application: performances and limitations
By Dominique TOURNIER, Pierre BROSSELARD, Pascal BEVILACQUA, Jean-François DE PALMA [View]
[Download]

Abstract: The performances and limitation of SiC JBS diodes used as clamping devices for SSCB have been investigated trough simulation and experimental measurements. The simulations evaluations are based on CAD and electro-thermal circuit modelling of packaged devices. The simulations have been done on a wide blocking voltage range, form 80V to 1.7kV. An optimal trade-off in terms of layout and avalanche capability has been found. A failure criterion in terms of power density has been established, linked to device top metal layers melting (around 500°C) and measured on commercial devices. Avalanche to Nominal current Ratio varies between 6 up to 10 depending on the manufacturer. A LTspice electro-thermal model allows to predict the required SiC devices area to achieve specific performances. Finally, a demonstrator of 1.2kV-2x50A-SOT227 SiC JBS clamping diode is presented.

EPE 2025 - DS1k: Active Devices and Components
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2025 - Conference > EPE 2025 - Topic 07: Semiconductor Devices and Packaging > EPE 2025 - DS1k: Active Devices and Components
	[return to parent folder]

	Characterization of an Integrated GaN Driver for Power Switching Applications By Benedikt KOHLHEPP, Houssam HALHOUL, Nick WIECZOREK, Xiaomeng GENG, Lars SCHELLHASE, Oliver HILT, Sibylle DIECKERHOFF	[View] [Download]
Abstract: Modern GaN-HEMTs require appropriate driving circuits to enable fast switching. Thus, monolithic integration of power switches and gate drivers is necessary. Therefore, this paper demonstrates a GaN driver to control a GaN power switch. Besides static and pulsed characterization, the driver's performance is validated through continuous switching tests, demonstrating effective operation with turn-on and turn-off times of an emulated load of 1.68 ns and 1.84 ns, respectively.

	High temperature characterizations of a monolithic 900 V GaN power device for current source inverter applications By Van-Sang NGUYEN, René ESCOFFIER, Stephane CATELLANI, Anthony BIER	[View] [Download]
Abstract: Based on the recent works [1-4] on the current source inverter for photovoltaic (PV) application with Silicon Carbide (SiC) devices, this work presents the design and the characterizations of a monolithic GaN (Gallium Nitride) device where the GaN transistor and the diode in series connection are built up on a single chip for a specific current source inverter topology. This work presents the details of this monolithic 900 V GaN device in the first section, and then the static characterizations by using of an automatic industrial equipment (B1506 from Keysight) with a high temperature thermostream will be shown in the second section. A specific double pulse test-bench is detailed for high temperature dynamic characterization with the high speed current and voltage probes, this monolithic GaN device can be heated-up locally up to 175°C by using an infrared beam station.

	Losses Evaluation on Parallel Diodes Using a Double Pulse Test Circuit By Gustavo HENN, Frédéric RAYMOND-LARUINA, Herminio DE OLIVEIRA FILHO, Tanguy PHULPIN	[View] [Download]
Abstract: This paper aims to optimize efficiency by combining diodes, such as SiC Schottky or PiN Si in parallel. For each combination, conduction and switching losses are estimated using datasheet in addition to double pulse test circuit validation. The parallelization of each diode is studied to propose the best configuration.

	Maximize advantages in hard and soft-switching applications with optimal use of a modern SiC MOSFET with low output capacitance By Jaeeul YEON, Syeda Qurat ul ain AKBAR, Qibin WU	[View] [Download]
Abstract: Silicon carbide (SiC) MOSFETs have superior properties at high voltage and high power compared to silicon (Si) devices in almost all aspects due to their material advantages such as three times larger band gap, three times larger thermal conductivity, ten times higher critical electric field, two times higher saturation velocity and so on. SiC MOSFETs can thus significantly improve the performance of the system. In addition to the well-known advantages of SiC MOSFETs over Si MOSFETs and IGBTs, a deeper understanding and right usage of SiC MOSFETs can help enhance device performance and maximize system value propositions. In this paper, a parameters-oriented approach is proposed to select the right SiC MOSFET device corresponding to the requirements of each application. The proposed approach has been validated by PLECS simulation results of representative hard and soft switching applications.

	Measurement Techniques of Threshold Voltage Shift and Recovery in GaN e-HEMTs By Burhan ETOZ, Arkadeep DEB, Jose ORTIZ-GONZALEZ, Layi ALATISE	[View] [Download]
Abstract: This paper presents two different techniques of threshold voltage shift (_VTH) and recovery characterisation in GaN e-HEMTs. The first technique applies a stressing gate voltage (VGS) of defined magnitude and duration and then measures a _VTH at different time intervals by shorting the gate-to-drain terminals of the e-HEMT while passing a sensing current trough the drain-source. In the second technique, after the VGS stress, a sensing current through the 3rd quadrant of the GaN e-HEMT is used to measure the 3rd quadrant voltage as an indicator of _VTH. Both measurements show the same trends. With positive VGS stress, _VTH is positive (due to electron capture at the p-GaN/AlGaN interface) and then becomes negative over time due to faster electron release than hole release. The magnitude of the initial positive _VTH is proportional to the VGS stress while the recovery rate is inversely proportional of VGS stress.

	Modelling of SiC and GaN Transistors Based on Pulsed S-Parameter Measurements By Martin HERGT, Bernhard HAMMER, Martin SACK, Lukas W. MAYER, Sebastian NIELEBOCK, Marc HILLER	[View] [Download]
Abstract: For the design of fast-switching inverters a precise model of power semiconductors is required. Based on pulsed S-parameter measurements in the frequency range of 2 MHz to 500 MHz a SiC MOSFET and a GaN HEMT have been characterized. As basis for precise modelling, measurements under varying load conditions have been taken for many operating points covering the pinch-off, ohmic, and active regions. The employed model to describe the transistor uses a circuit comprising 12 circuit elements. Thereby, the elements of the intrinsic transistor vary with the transistor's operating point and parameters describing the influence of the package are considered to be constant. The model parameters have been adjusted iteratively. A comparison of the obtained model with the original S-parameter measurements exhibits an excellent match.

	Parasitic Capacitances Effect on Transient Current Sharing in Parallel Connection of GaN FETs By Salvatore MUSUMECI, Vincenzo BARBA, Michele PASTORELLI, Marco PALMA	[View] [Download]
Abstract: The paper deals with the impact of parasitic capacitance on the switching operation of GaN FET devices in parallel connection. A suitable experimental board has been developed to investigate the switching transient current share features for several GaN FETs connected in parallel to perform a single high-current switch. Every device can be driven independently, and a source shunt per each GaN FET monitors the transistor current. Simulation runs and experimental tests show the switching mechanism and parameters involved in the transients' current share. The paper aims to give insights into the designing boards of paralleled GaN FETs regarding the influence of parasitic capacitances in the transient current peak distribution to find the maximum parasitic capacitance reachable without overcoming the limit of impulsive device current. The study contributes to developing reliable power modules made of several GaN FETs in parallel connection.

	SiC MOSFET turn-off overvoltage measurement By Mikel GALDEANO, Ernesto Luis BARRIOS, David ELIZONDO-MARTINEZ, Pablo SANCHIS	[View] [Download]
Abstract: Selecting the appropriate measurement system is crucial in power electronics. This is especially important during MOSFET's turn-off process, where it is essential to measure the voltage rise and accurately capture the peak overvoltage. During turn-off, the interaction between the MOSFET and the parasitic element of the PCB creates a resonance. This phenomenon leads to an overvoltage, which peaks at the resonance frequency and can potentially damage the device. This paper discusses the characteristics of the measurement system needed to capture the peak overvoltage accurately. A step-by-step guide is proposed to ensure the correct selection of the probe and its correct use. This guide is experimentally validated on a three-level converter, where drain-source voltage measurements have been performed with and without a ground reference. The drain to source measurement method proposed in this paper is accurate, cost-effective and capable of minimizing induced noise.

	Static vs. Dynamic Characterization of p-GaN HEMTs: Discrepancies in Electrical Characteristics and their Dependence on Bias History By Ludovic ROCHE, David TRÉMOUILLES, Emmanuel MARCAULT, Corinne ALONSO	[View] [Download]
Abstract: Quasi-static electrical characteristics of p-GaN HEMTs fluctuate with bias history. This study evidences that dynamic operation is fortunately highly reproducible without pre-conditioning. The original experimental setup highlights that quasi-static data alone is insufficient for modeling dynamic behavior, while allowing precise detection of discrepancies, enabling improved transient modeling.

	Test Setup for Measuring the Impact of Gate Stress on a GaN-HEMT's Output Characteristic By Daniel BREIDENSTEIN, Sophia ROESEL, Benedikt KOHLHEPP, Thomas DUERBAUM	[View] [Download]
Abstract: Precisely estimating conduction losses requires knowledge of the device's output characteristic in the ohmic region. For GaN-HEMTs, it dynamically depends on time, temperature, and applied biases. To study the impact of gate bias over time, a transient measurement approach is applied, that can acquire the start of the output characteristic with a single pulse. This ensures neglectable impact of temperature changes and trapping state on the single measurement. In addition, the short acquisition time allows studying the impact of the bias in the milliseconds range. Therefore, the measurement pulses are altered with stress intervals. While reference measurements for a traditional Si-MOSFET under constant gate bias show almost no change in the output characteristic over time, test results for a commercial GaN-HEMT reveal changes for low gate voltages. This demonstrates that the user should at least be aware of such trapping problems effecting measurements, which may lead to differences in characterization and application.

	Using SiC JBS diode as voltage clamping in SSCB application: performances and limitations By Dominique TOURNIER, Pierre BROSSELARD, Pascal BEVILACQUA, Jean-François DE PALMA	[View] [Download]
Abstract: The performances and limitation of SiC JBS diodes used as clamping devices for SSCB have been investigated trough simulation and experimental measurements. The simulations evaluations are based on CAD and electro-thermal circuit modelling of packaged devices. The simulations have been done on a wide blocking voltage range, form 80V to 1.7kV. An optimal trade-off in terms of layout and avalanche capability has been found. A failure criterion in terms of power density has been established, linked to device top metal layers melting (around 500°C) and measured on commercial devices. Avalanche to Nominal current Ratio varies between 6 up to 10 depending on the manufacturer. A LTspice electro-thermal model allows to predict the required SiC devices area to achieve specific performances. Finally, a demonstrator of 1.2kV-2x50A-SOT227 SiC JBS clamping diode is presented.