EPE Association: EPE 2023 - DS2c: System Integration, Packaging & Thermal Management

EPE 2023 - DS2c: System Integration, Packaging & Thermal Management
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2023 ECCE Europe - Conference > EPE 2023 - Topic 01: Devices, Packaging and System Integration > EPE 2023 - DS2c: System Integration, Packaging & Thermal Management

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   A High Power Density SiC MOSFET Inverter Design and Thermal Validation for EV Traction Application
By Kaushik MIRDODDI, Gopikrishnan K, Abhrodip CHAUDHURY, Soumya Shubhra NAG, Sumit Kumar PRAMANICK, Anandarup DAS, Mike MORIANZ, Gerald WEIS, Thomas KOECK, Johannes STAHR, Guenther MAIER [View]
[Download]

Abstract: This paper addresses the design procedures and challenges of developing compact, high-density inverters by fabricating a half-bridge module using PCB embedded technology. The modules are constructed by placing 1.2 kV, 100 A MOSFET dies in the inner layers of the PCB, and the electrical connection for the dies is achieved using copper layers and micro-vias. The electrothermal analysis performed using ANSYS Electromagnetic suite demonstrates a low parasitic power loop inductanceof 4.25 nH and a junction temperature of less than 140 _C, indicating the efficacy of the design. A thermal test bench was set up, to validate the thermal simulation results.

   Active Thermal Control of a DC-DC Converter Using Dynamic Gate-drive for Reliability Improvement
By Farzad HOSSEINABADI, Olcay BAY, Sachin Kumar BHOI, Sajib CHAKRABORTY, Mohamed EL BAGHDADI, Omar HEGAZY [View]
[Download]

Abstract: In this article, a new approach for smoothing junction temperature fluctuations through active thermal control is proposed. By utilizing a current-source gate drive and controlling switching transition, switching losses can be regulated in a way to control junction temperature swing which is a dominant reason of wear-out failure mechanisms in MOSFETs. The simulation results indicate a 29\% increase in lifetime. Additionally, the experimental results demonstrate the capability of this approach to control the junction temperature of a MOSFET effectively.

   Analysis of inhomogeneous temperature distribution in power modules for different cooling systems and the influence on lifetime consumption
By Michael GLEISSNER, Mark-M. BAKRAN [View]
[Download]

Abstract: The temperature distribution in an IGBT module with 24 parallel chips is examined using an infrared temperature camera. Water and air cooling have different temperature distributions, but the difference between the hottest and coldest chips are similar at an equal mean temperature of all chips. The variation of the forward characteristic of the individual chips only has a minor influence on the temperature distribution.

   Comparative Thermal Analysis of Cooling Methods for Dual Inverter Applications in Electric Vehicles
By Gamze EGIN MARTIN, Farzad HOSSEINABADI, Sajib CHAKRABORTY, Mohamed EL BAGHDADI, Claudio ROMANO, Maurizio TRANCHERO, Omar HEGAZY [View]
[Download]

Abstract: Electric vehicles (EVs) have gained global attention as a solution to climate change and pollution caused by internal combustion engine vehicles (ICEVs). However, the limited driving range and long charging time pose challenges for EVs. Higher power density and efficiency in power electronic systems can increase the driving range of EVs. Advancements in power electronics for EVs have led to higher power density integration and smaller components. Therefore, effective thermal management solutions are crucial to maintaining device temperatures within acceptable limits for higher powerdensities. This research aims to investigate and compare the thermal cooling efficiency and pressure drop of different liquid cooling methods (serial and parallel cooling) for dual inverter applications based on SiC MOSFETs. Extensive evaluations have been conducted using Ansys Fluent software for Computational Fluid Dynamics (CFD) simulations. The study emphasizes the benefits of parallelcooling with reduced pressure drop, offering enhanced heat dissipation, higher power density, and optimized thermal management.

   Experimental verification of the AC resistance effect in Insulated Metal Substrate IMS based power converters
By Iosu AIZPURU, Miguel LAJAS, Asier ARRUTI, Eneko AGIRREZABALA, Miguel SANZ, Francisco PEREZ, Mikel MAZUELA [View]
[Download]

Abstract: Insulated Metal Substrate (IMS) based power converters are an excellent solution for thermal dissipation of power converters, but they suffer for limited layer options generating parasitic elements specially in High Frequency. The paper analyses and proposes experimental verification of IMS AC resistance in High Frequency power converter applications. The developed test bench can generate high current high frequency electrical signals in order to excite the IMS board parasitic AC resistances. The experimental validation highlights the importance of PCB lay-out in high frequency IMS boards where big area current loops and low copper areas increase significantly the resistance of the board. The developed tests verify a significant AC resistance effect in IMS boards with a temperature increase 4 times bigger at 500 kHz switching frequency than the equivalent DC current.

   Junction temperature calculation on Power Modules, based on the transient Thermal Impedance for Mission Profile evaluation in the EV Traction Inverter
By Emanuela PRIVITERA, Marco PAPASERIO, Daniela Grazia CAVALLARO [View]
[Download]

Abstract: The thermal impedance at steady state is generally used for fast evaluation of Mission Profiles, whereas rigorous estimation in transient mode represents a challenge for huge calculation time. This paper describes a methodology for calculating the junction temperature by means of transient thermal impedance with low computation time and power.

   Packaging of 20 kV Double-Side Cooled Silicon Carbide Diode Module With Electrical Insulation Enhanced by a Polymer-Nanoparticle Coating
By Zichen ZHANG, Carl NICHOLAS, Emmanuel ARRIOLA, Justin LYNCH, Nick YUN, Adam MORGAN, Woongje SUNG, Khai NGO, Guo-Quan LU [View]
[Download]

Abstract: To address the insulation challenges in packaging medium-voltage silicon carbide power devices, a package design for a 20-kV silicon carbide diode was developed. This design uses a nonlinear resistive polymer-nanoparticle composite to enhance insulation without sacrificing thermal performance. The 'sandwich' structure, involving diodes connected between direct-bonded copper substrates, reduces parasitic inductance (inf.4.5 nH) in a wirebond-less design. This configuration results in a 41\% decrease in junction-to-case thermal resistance, according to thermal simulations. Coating electrode triple points with the resistive composite reduces electric field stress. Experimental tests revealed a 96\% increase in the partial discharge inception voltage of substrates from 15.6 kV to 30.6 kV. Scaled-down packages with 15 kV silicon carbide diodes was fabricated and tested for validation.

   PCB Layout Parasitics Extraction of a GaN Half-Bridge: Simulation and Experimental Validation
By Benedikt KOHLHEPP, Samuel FABER, Daniel KÃœBRICH, Thomas DÃœRBAUM [View]
[Download]

Abstract: Commutation loop inductance is on everyone's lips in power electronics, due the relevance for switching transitions and switching losses. In most cases, this inductance is obtained by using numerical field simulations. However, confidence in the simulation results requires validation by measurements. Especially for designs employing wide bandgap semiconductors, minimized commutation loop inductance is crucial for full performance of the semiconductors. Applying optimized packages and PCB layouts results in commutation loop inductances below 1 nH, which makes its experimental extraction challenging. Therefore, the paper studies a method for commutation inductance measurement based on a resonance of a modified DC-link capacitor with this inductance. The measurement of a GaN-half-bridge's commutation loop complies with results from simulation, demonstrating that the measurement method is applicable for commutation inductance in sub-nH range.

   Temperature Monitoring of Multi-Chip SiC MOSFET Modules: On-Chip RTDs vs. VSD(T)
By Nick BAKER, Szymon BECZKOWSKI, Francesco IANNUZZO, Andy LEMMON, John AUSTIN, Lauren OSTRANDER [View]
[Download]

Abstract: In this paper we compare on-chip RTD sensors and the VSD(T) method for temperature measurement of multi-chip SiC MOSFET modules. We find that the average temperature across multiple chips measured via on-chip RTDs correlates closely with the VSD(T). However, the minimum and maximum chip temperature changes according to the module's operating conditions. This cannot be detected by the VSD(T) method. In a half-bridge module with 4-chips per switch position, we apply two operating conditions that give the same measured temperature via VSD(T). The maximum chip temperature, measured via the on-chip RTD, deviates over 5°C. This may have implications for power cycling lifetime on multi-chip power modules. We also demonstrate the use of the on-chip RTDs in an IGBT inverter.

   Thermal Characterization of Packaged SiC Devices for High-Temperature Applications
By Varaha Satya Bharath KURUKURU, Md Nazmul HASAN, Roberto PETRELLA [View]
[Download]

Abstract: Effective thermal management is crucial for the high-temperature operation of silicon carbide (SiC) devices, as the available thermal margin for these devices is limited. In addition, the temperature affects the thermal properties of packaging materials, such as thermal conductivity and specific heat, leading to variations in the thermal performance of the packaged semiconductor. Thus, precise thermal analysis is necessary to ensure steady and dependable operation of SiC devices in high-temperature environments. To fulfill this need, this study introduces the thermal characterization of packaged SiC devices for high-temperature applications.

EPE 2023 - DS2c: System Integration, Packaging & Thermal Management
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2023 ECCE Europe - Conference > EPE 2023 - Topic 01: Devices, Packaging and System Integration > EPE 2023 - DS2c: System Integration, Packaging & Thermal Management
	[return to parent folder]

	A High Power Density SiC MOSFET Inverter Design and Thermal Validation for EV Traction Application By Kaushik MIRDODDI, Gopikrishnan K, Abhrodip CHAUDHURY, Soumya Shubhra NAG, Sumit Kumar PRAMANICK, Anandarup DAS, Mike MORIANZ, Gerald WEIS, Thomas KOECK, Johannes STAHR, Guenther MAIER	[View] [Download]
Abstract: This paper addresses the design procedures and challenges of developing compact, high-density inverters by fabricating a half-bridge module using PCB embedded technology. The modules are constructed by placing 1.2 kV, 100 A MOSFET dies in the inner layers of the PCB, and the electrical connection for the dies is achieved using copper layers and micro-vias. The electrothermal analysis performed using ANSYS Electromagnetic suite demonstrates a low parasitic power loop inductanceof 4.25 nH and a junction temperature of less than 140 _C, indicating the efficacy of the design. A thermal test bench was set up, to validate the thermal simulation results.

	Active Thermal Control of a DC-DC Converter Using Dynamic Gate-drive for Reliability Improvement By Farzad HOSSEINABADI, Olcay BAY, Sachin Kumar BHOI, Sajib CHAKRABORTY, Mohamed EL BAGHDADI, Omar HEGAZY	[View] [Download]
Abstract: In this article, a new approach for smoothing junction temperature fluctuations through active thermal control is proposed. By utilizing a current-source gate drive and controlling switching transition, switching losses can be regulated in a way to control junction temperature swing which is a dominant reason of wear-out failure mechanisms in MOSFETs. The simulation results indicate a 29\% increase in lifetime. Additionally, the experimental results demonstrate the capability of this approach to control the junction temperature of a MOSFET effectively.

	Analysis of inhomogeneous temperature distribution in power modules for different cooling systems and the influence on lifetime consumption By Michael GLEISSNER, Mark-M. BAKRAN	[View] [Download]
Abstract: The temperature distribution in an IGBT module with 24 parallel chips is examined using an infrared temperature camera. Water and air cooling have different temperature distributions, but the difference between the hottest and coldest chips are similar at an equal mean temperature of all chips. The variation of the forward characteristic of the individual chips only has a minor influence on the temperature distribution.

	Comparative Thermal Analysis of Cooling Methods for Dual Inverter Applications in Electric Vehicles By Gamze EGIN MARTIN, Farzad HOSSEINABADI, Sajib CHAKRABORTY, Mohamed EL BAGHDADI, Claudio ROMANO, Maurizio TRANCHERO, Omar HEGAZY	[View] [Download]
Abstract: Electric vehicles (EVs) have gained global attention as a solution to climate change and pollution caused by internal combustion engine vehicles (ICEVs). However, the limited driving range and long charging time pose challenges for EVs. Higher power density and efficiency in power electronic systems can increase the driving range of EVs. Advancements in power electronics for EVs have led to higher power density integration and smaller components. Therefore, effective thermal management solutions are crucial to maintaining device temperatures within acceptable limits for higher powerdensities. This research aims to investigate and compare the thermal cooling efficiency and pressure drop of different liquid cooling methods (serial and parallel cooling) for dual inverter applications based on SiC MOSFETs. Extensive evaluations have been conducted using Ansys Fluent software for Computational Fluid Dynamics (CFD) simulations. The study emphasizes the benefits of parallelcooling with reduced pressure drop, offering enhanced heat dissipation, higher power density, and optimized thermal management.

	Experimental verification of the AC resistance effect in Insulated Metal Substrate IMS based power converters By Iosu AIZPURU, Miguel LAJAS, Asier ARRUTI, Eneko AGIRREZABALA, Miguel SANZ, Francisco PEREZ, Mikel MAZUELA	[View] [Download]
Abstract: Insulated Metal Substrate (IMS) based power converters are an excellent solution for thermal dissipation of power converters, but they suffer for limited layer options generating parasitic elements specially in High Frequency. The paper analyses and proposes experimental verification of IMS AC resistance in High Frequency power converter applications. The developed test bench can generate high current high frequency electrical signals in order to excite the IMS board parasitic AC resistances. The experimental validation highlights the importance of PCB lay-out in high frequency IMS boards where big area current loops and low copper areas increase significantly the resistance of the board. The developed tests verify a significant AC resistance effect in IMS boards with a temperature increase 4 times bigger at 500 kHz switching frequency than the equivalent DC current.

	Junction temperature calculation on Power Modules, based on the transient Thermal Impedance for Mission Profile evaluation in the EV Traction Inverter By Emanuela PRIVITERA, Marco PAPASERIO, Daniela Grazia CAVALLARO	[View] [Download]
Abstract: The thermal impedance at steady state is generally used for fast evaluation of Mission Profiles, whereas rigorous estimation in transient mode represents a challenge for huge calculation time. This paper describes a methodology for calculating the junction temperature by means of transient thermal impedance with low computation time and power.

	Packaging of 20 kV Double-Side Cooled Silicon Carbide Diode Module With Electrical Insulation Enhanced by a Polymer-Nanoparticle Coating By Zichen ZHANG, Carl NICHOLAS, Emmanuel ARRIOLA, Justin LYNCH, Nick YUN, Adam MORGAN, Woongje SUNG, Khai NGO, Guo-Quan LU	[View] [Download]
Abstract: To address the insulation challenges in packaging medium-voltage silicon carbide power devices, a package design for a 20-kV silicon carbide diode was developed. This design uses a nonlinear resistive polymer-nanoparticle composite to enhance insulation without sacrificing thermal performance. The 'sandwich' structure, involving diodes connected between direct-bonded copper substrates, reduces parasitic inductance (inf.4.5 nH) in a wirebond-less design. This configuration results in a 41\% decrease in junction-to-case thermal resistance, according to thermal simulations. Coating electrode triple points with the resistive composite reduces electric field stress. Experimental tests revealed a 96\% increase in the partial discharge inception voltage of substrates from 15.6 kV to 30.6 kV. Scaled-down packages with 15 kV silicon carbide diodes was fabricated and tested for validation.

	PCB Layout Parasitics Extraction of a GaN Half-Bridge: Simulation and Experimental Validation By Benedikt KOHLHEPP, Samuel FABER, Daniel KÃœBRICH, Thomas DÃœRBAUM	[View] [Download]
Abstract: Commutation loop inductance is on everyone's lips in power electronics, due the relevance for switching transitions and switching losses. In most cases, this inductance is obtained by using numerical field simulations. However, confidence in the simulation results requires validation by measurements. Especially for designs employing wide bandgap semiconductors, minimized commutation loop inductance is crucial for full performance of the semiconductors. Applying optimized packages and PCB layouts results in commutation loop inductances below 1 nH, which makes its experimental extraction challenging. Therefore, the paper studies a method for commutation inductance measurement based on a resonance of a modified DC-link capacitor with this inductance. The measurement of a GaN-half-bridge's commutation loop complies with results from simulation, demonstrating that the measurement method is applicable for commutation inductance in sub-nH range.

	Temperature Monitoring of Multi-Chip SiC MOSFET Modules: On-Chip RTDs vs. VSD(T) By Nick BAKER, Szymon BECZKOWSKI, Francesco IANNUZZO, Andy LEMMON, John AUSTIN, Lauren OSTRANDER	[View] [Download]
Abstract: In this paper we compare on-chip RTD sensors and the VSD(T) method for temperature measurement of multi-chip SiC MOSFET modules. We find that the average temperature across multiple chips measured via on-chip RTDs correlates closely with the VSD(T). However, the minimum and maximum chip temperature changes according to the module's operating conditions. This cannot be detected by the VSD(T) method. In a half-bridge module with 4-chips per switch position, we apply two operating conditions that give the same measured temperature via VSD(T). The maximum chip temperature, measured via the on-chip RTD, deviates over 5°C. This may have implications for power cycling lifetime on multi-chip power modules. We also demonstrate the use of the on-chip RTDs in an IGBT inverter.

	Thermal Characterization of Packaged SiC Devices for High-Temperature Applications By Varaha Satya Bharath KURUKURU, Md Nazmul HASAN, Roberto PETRELLA	[View] [Download]
Abstract: Effective thermal management is crucial for the high-temperature operation of silicon carbide (SiC) devices, as the available thermal margin for these devices is limited. In addition, the temperature affects the thermal properties of packaging materials, such as thermal conductivity and specific heat, leading to variations in the thermal performance of the packaged semiconductor. Thus, precise thermal analysis is necessary to ensure steady and dependable operation of SiC devices in high-temperature environments. To fulfill this need, this study introduces the thermal characterization of packaged SiC devices for high-temperature applications.