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   Packaging of 20 kV Double-Side Cooled Silicon Carbide Diode Module With Electrical Insulation Enhanced by a Polymer-Nanoparticle Coating   [View] 
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 Author(s)   Zichen ZHANG, Carl NICHOLAS, Emmanuel ARRIOLA, Justin LYNCH, Nick YUN, Adam MORGAN, Woongje SUNG, Khai NGO, Guo-Quan LU 
 Abstract   To address the insulation challenges in packaging medium-voltage silicon carbide power devices, a package design for a 20-kV silicon carbide diode was developed. This design uses a nonlinear resistive polymer-nanoparticle composite to enhance insulation without sacrificing thermal performance. The 'sandwich' structure, involving diodes connected between direct-bonded copper substrates, reduces parasitic inductance (inf.4.5 nH) in a wirebond-less design. This configuration results in a 41\% decrease in junction-to-case thermal resistance, according to thermal simulations. Coating electrode triple points with the resistive composite reduces electric field stress. Experimental tests revealed a 96\% increase in the partial discharge inception voltage of substrates from 15.6 kV to 30.6 kV. Scaled-down packages with 15 kV silicon carbide diodes was fabricated and tested for validation. 
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Filename:0088-epe2023-full-18235660.pdf
Filesize:513 KB
 Type   Members Only 
 Date   Last modified 2023-09-24 by System