EPE Association: EPE 2009 - Subtopic 01-5 - DS: 'Field Controlled Si Power Devices'

EPE 2009 - Subtopic 01-5 - DS: 'Field Controlled Si Power Devices'
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2009 - Conference > EPE 2009 - Topic 01: 'Active Devices' > EPE 2009 - Subtopic 01-5 - DS: 'Field Controlled Si Power Devices'

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   3-level IGBT modules with Trench Gate IGBT and their thermal analysis in UPS, PFC and PV operation modes
By Marco HONSBERG, Thomas RADKE [View]
[Download]

Abstract: Utilizing 3-level topology for less than 800V of DC-link voltage where â€œstandardâ€ 2- level 1200V Vces â€“ class IGBT modules would be sufficient basically is a result of an inherent advantage of switching loss versus DC-loss of 3-level topology. The control of the semiconductors in a 3-level NPC topology employs a set of totally 12 control signals which are generated by ÂµC or DSP or FPGA. A back to back 2-level / 3-level inverter has been built to circulate power performing arbitrary load conditions to analyze the thermal dissipation of the semiconductors. This thermal analysis utilizes an IR camera o perform an in situ measurement and allows precise modeling of thermal and electrical parameter. Once this experimental platform has been calibrated, the loss on each semiconductor chip can acquired and compared with the simulated result. Hence, tuning of the model parameter becomes possible. Besides the thermal investigation the approach of using IGBT module having specifically integrated Real Time current Controller (RTC) and their contribution to turn off short circuit (SC) situations safely by forcing to keep the SC turn off sequence of the 3-level NPC leg.

   Analytical Approach of Saturation Voltage instability in High-Speed IGBTs
By MITSURU KANEDA [View]
[Download]

Abstract: High speed IGBT utilizing EB irradiation process for lifetime control of active layer have been developed for industry applications, home use applications, and so on. The saturation voltage instability in such IGBT under the high current density condition for long-time is one of the remarkable problems and is inevitable obstacles to be overcome. We have investigated the dependence on the process condition and on the stress condition of this phenomenon. We have evaluated the I-V characteristics, switching characteristics, threshold voltage, and leakage current to accompany the saturation voltage instability. Analysis using the cathodeluminescence methods has been also performed to suppress this problem.

   Design Considerations on Field-Stop Layer Processing in a Trench-Gate IGBT
By Antonino Sebastiano ALESSANDRIA, Leonardo FRAGAPANE, Giuseppe MORALE [View]
[Download]

Abstract: In recent years a new device concept appeared in the IGBT technology. It is a structure between a PT and an NPT device, with a low-doped emitter, where the fundamental role is played by the Field-Stop layer. In this paper we fixed some considerations about a proper design of this layer. Some simulated and real electrical characteristics of a trench-gate emitter-implanted IGBT will be shown and correlated to the Field-Stop layer process parameters.

   Design Specification of a 270 V 100 A Solid-State Power Controller Suitable for Aerospace Applications
By Mohamed ABD ELRAZEK, Philip MAWBY [View]
[Download]

Abstract: In this paper, a 270V solid state power controller (SSPC) with 100A nominal current rating is proposed. In order to realize the size and weight constraints of the SSPC, several MOSFETs in parallel are used, which must be capable of handling fault conditions such as, short-circuit and lightning strikes. In Here simulation work has been carried out using the state of the art of electro-thermal models of COOLMOS switches. SABER has been used to model this novel implementation, and using this approach it is possible to optimize the MOSFET areas, and the overall SSPC size.

   Field Balanced SG-RSO structure showing tremendous potential for low voltage Trench MOSFETs
By Chin Foong TONG, Philip Andrew MAWBY, James COVINGTON [View]
[Download]

Abstract: This paper presents a 30V range â€˜Field Balancedâ€™ Split-Gate RSO (Resurf Stepped Oxide) MOSFET showing extremely low Qgd of 1.0 nC mm^2 for the first time. By introducing a low doped region on an optimised 30V Split-Gate RSO MOSFET, the Figure of Merit (FOM) improves from 8.09 nC to around 6.40 mohm nC. From this investigation, it has been demonstrated that the â€˜Field Balancedâ€™ on a a Split-Gate structure can give a good RdsON vs Qgd trade off. The exceptionally low Qgd will allow the â€˜Field Balancedâ€™ structure to achieve a good efficiency even in high switching frequency converter.

   LUDMOS transistors optimization on a 0.18m SOI CMOS technology
By Ignacio CORTES [View]
[Download]

Abstract: This paper is focused on the design and optimization of power LDMOS transistors with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 Âµm SOI-CMOS technology. Different LDMOS structures which allow breakdown voltages (VBR) higher than 120 V have been analyzed by means of 2D and 3D TCAD simulations. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is compared in terms of the main static (specific on-state resistance vs breakdown voltage (Ron-sp/VBR) trade-off) and dynamic (Gate-to-Drain charge (Qgd) and Gate charge (Qg) vs Ron trade-off) characteristics. The influence of some drift region design parameters, such as the Poly-gate (LPoly) and STI (LSTI) lengths, are also exhaustively analyzed in this work

   Numerical Analysis of Destruction Modes in IGBT Chips
By Ulla KNIPPER, Gerhard WACHUTKA, Frank PFIRSCH, Thomas RAKER, Josef NIEDERMEYR [View]
[Download]

Abstract: In IGBTs avalanche breakdown usually sets on in the edge termination structure. In consequence of electrical crosstalk, the destruction mechanism in very thin devices is confined to the neighboring cells in the active part of the chip. Thus, in order to achieve the largest possible safe-operating area, design optimization has to focus on the edge termination structure and the neighboring active cells in its vicinity.

   Obvious Suppression of Performance Degradation Induced by Thermal Effect in SOI Power LDMOSFETs Using Accumulation Mode Device Structure
By Weitao CHENG, Akinobu TERAMOTO, Tadahiro OHMI [View]
[Download]

Abstract: In this paper, we demonstrate that the advantages of obvious improvement o f the mobility and current drivability at high temperatures and the greatly suppressed self-heating effects in accumulation mode SOI power LDMOSFETs. We reveal the mechanisms of these advantages are resulted from the bulk current and accumulation mode device structure and propose that the accumulation mode device structure is very useful to realize high performance SOI power LDMOSFETs.

   Optimization of the Stray Inductance in Three-Phase MOSFET Power Modules Aided by means of PEEC Simulation
By Ole MÃœHLFELD, F.W. FUCHS [View]
[Download]

Abstract: Minimum stray inductances are of high importance for power modules and stacks of converters. This paper describes the optimization of the stray inductance for a compact DBC based three-phase power module for use in 5 to 20 kW converters for automotive application. The inductances of different DBC layouts and mounting technologies are compared and optimized, including chip connection with soldered tapes. The simulated values are compared with measurement results.

   Passive Turn-On Process of IGBTs in Matrix Converter Applications
By Roman BABURSKE, Daniel DOMES, Josef LUTZ, Wilfried HOFMANN [View]
[Download]

Abstract: The passive turn-on of IGBTs occurs in Matrix converter applications. This paper analyzes different IGBT-types in terms of passive turn-on. Measurements of passive turn-ons of different IGBT-types are shown and compared with diode turn-ons. The dependency of the turn-on voltage peak on the temperature, the gate resistance and the current is investigated. The results are analyzed by numerical device simulations.

   Performances of MOS-Gated GTO in High Voltage Power Applications
By CESARE RONSISVALLE, Annunziata SANSEVERINO, Vicenzo ENEA, Carmine ABBATE, Giovanni BUSATTO [View]
[Download]

Abstract: In this paper we present a comparative study between the characteristics of the MOS-Gated GTO, a new power semiconductor device, and the IGBT having the same n-n+p+ vertical structure. The blocking voltage of the analyzed devices ranges between 1.2kV and 4.5kV. Simulation results show that the MOS-GTO exhibits a much better trade-off between on state and switching characteristics than the IGBT particularly in the range of the high blocking voltages. The excellent performances of the MOS-GTO make it a very promising device for high voltage power applications.

   The Effects of the Stray Elements on the Failure of Parallel Connected IGBTs during Turn-Off
By Carmine ABBATE, Giovanni BUSATTO, Francesco IANNUZZO [View]
[Download]

Abstract: The very good performances of IGBT modules in terms of current robustness and thermal overstress can be used on power converters in order to obtain cost and weight reduction. Moreover, in order to develop higher performance devices, it is very important to discover and understand instable failure mechanisms that can occur during IGBT operations. The paper presents an experimental characterization aimed to understand the effects of the stray elements of the connecting circuit on the failure of parallel connected IGBT during turn-off at very high collector current with very low gate resistance. The failure mechanism can be associated to the unequal distribution of the current among the devices whose effects are particularly enhanced by the combination of gate resistance and stray inductance in the emitter circuit. The experimental characterization has been executed by means of a non-destructive tester set-up, in order to reduce the number of required devices.

   Trench isolation technique for Reverse Blocking IGBT using Boron Nitride doping wafers
By MIQUEL VELLVEHI, JOSE LUIS GALVEZ, XAVIER PERPINYA, XAVIER JORDA, PHILIPPE GODIGNON, JOSE MILLAN [View]
[Download]

Abstract: A new fabrication process for IGBT devices with reverse blocking capability (RB-IGBT) is presented in this paper. The trench isolation technique which provides the reverse blocking capability has been implemented using solid source as doping technique (Boron doping wafers), resulting in a low-cost process in both starting material and time-consuming aspects. The feasibility of the fabrication technique has been demonstrated with the electrical measurements of the fabricated devices.

EPE 2009 - Subtopic 01-5 - DS: 'Field Controlled Si Power Devices'
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2009 - Conference > EPE 2009 - Topic 01: 'Active Devices' > EPE 2009 - Subtopic 01-5 - DS: 'Field Controlled Si Power Devices'
	[return to parent folder]

	3-level IGBT modules with Trench Gate IGBT and their thermal analysis in UPS, PFC and PV operation modes By Marco HONSBERG, Thomas RADKE	[View] [Download]
Abstract: Utilizing 3-level topology for less than 800V of DC-link voltage where â€œstandardâ€ 2- level 1200V Vces â€“ class IGBT modules would be sufficient basically is a result of an inherent advantage of switching loss versus DC-loss of 3-level topology. The control of the semiconductors in a 3-level NPC topology employs a set of totally 12 control signals which are generated by ÂµC or DSP or FPGA. A back to back 2-level / 3-level inverter has been built to circulate power performing arbitrary load conditions to analyze the thermal dissipation of the semiconductors. This thermal analysis utilizes an IR camera o perform an in situ measurement and allows precise modeling of thermal and electrical parameter. Once this experimental platform has been calibrated, the loss on each semiconductor chip can acquired and compared with the simulated result. Hence, tuning of the model parameter becomes possible. Besides the thermal investigation the approach of using IGBT module having specifically integrated Real Time current Controller (RTC) and their contribution to turn off short circuit (SC) situations safely by forcing to keep the SC turn off sequence of the 3-level NPC leg.

	Analytical Approach of Saturation Voltage instability in High-Speed IGBTs By MITSURU KANEDA	[View] [Download]
Abstract: High speed IGBT utilizing EB irradiation process for lifetime control of active layer have been developed for industry applications, home use applications, and so on. The saturation voltage instability in such IGBT under the high current density condition for long-time is one of the remarkable problems and is inevitable obstacles to be overcome. We have investigated the dependence on the process condition and on the stress condition of this phenomenon. We have evaluated the I-V characteristics, switching characteristics, threshold voltage, and leakage current to accompany the saturation voltage instability. Analysis using the cathodeluminescence methods has been also performed to suppress this problem.

	Design Considerations on Field-Stop Layer Processing in a Trench-Gate IGBT By Antonino Sebastiano ALESSANDRIA, Leonardo FRAGAPANE, Giuseppe MORALE	[View] [Download]
Abstract: In recent years a new device concept appeared in the IGBT technology. It is a structure between a PT and an NPT device, with a low-doped emitter, where the fundamental role is played by the Field-Stop layer. In this paper we fixed some considerations about a proper design of this layer. Some simulated and real electrical characteristics of a trench-gate emitter-implanted IGBT will be shown and correlated to the Field-Stop layer process parameters.

	Design Specification of a 270 V 100 A Solid-State Power Controller Suitable for Aerospace Applications By Mohamed ABD ELRAZEK, Philip MAWBY	[View] [Download]
Abstract: In this paper, a 270V solid state power controller (SSPC) with 100A nominal current rating is proposed. In order to realize the size and weight constraints of the SSPC, several MOSFETs in parallel are used, which must be capable of handling fault conditions such as, short-circuit and lightning strikes. In Here simulation work has been carried out using the state of the art of electro-thermal models of COOLMOS switches. SABER has been used to model this novel implementation, and using this approach it is possible to optimize the MOSFET areas, and the overall SSPC size.

	Field Balanced SG-RSO structure showing tremendous potential for low voltage Trench MOSFETs By Chin Foong TONG, Philip Andrew MAWBY, James COVINGTON	[View] [Download]
Abstract: This paper presents a 30V range â€˜Field Balancedâ€™ Split-Gate RSO (Resurf Stepped Oxide) MOSFET showing extremely low Qgd of 1.0 nC mm^2 for the first time. By introducing a low doped region on an optimised 30V Split-Gate RSO MOSFET, the Figure of Merit (FOM) improves from 8.09 nC to around 6.40 mohm nC. From this investigation, it has been demonstrated that the â€˜Field Balancedâ€™ on a a Split-Gate structure can give a good RdsON vs Qgd trade off. The exceptionally low Qgd will allow the â€˜Field Balancedâ€™ structure to achieve a good efficiency even in high switching frequency converter.

	LUDMOS transistors optimization on a 0.18m SOI CMOS technology By Ignacio CORTES	[View] [Download]
Abstract: This paper is focused on the design and optimization of power LDMOS transistors with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 Âµm SOI-CMOS technology. Different LDMOS structures which allow breakdown voltages (VBR) higher than 120 V have been analyzed by means of 2D and 3D TCAD simulations. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is compared in terms of the main static (specific on-state resistance vs breakdown voltage (Ron-sp/VBR) trade-off) and dynamic (Gate-to-Drain charge (Qgd) and Gate charge (Qg) vs Ron trade-off) characteristics. The influence of some drift region design parameters, such as the Poly-gate (LPoly) and STI (LSTI) lengths, are also exhaustively analyzed in this work

	Numerical Analysis of Destruction Modes in IGBT Chips By Ulla KNIPPER, Gerhard WACHUTKA, Frank PFIRSCH, Thomas RAKER, Josef NIEDERMEYR	[View] [Download]
Abstract: In IGBTs avalanche breakdown usually sets on in the edge termination structure. In consequence of electrical crosstalk, the destruction mechanism in very thin devices is confined to the neighboring cells in the active part of the chip. Thus, in order to achieve the largest possible safe-operating area, design optimization has to focus on the edge termination structure and the neighboring active cells in its vicinity.

	Obvious Suppression of Performance Degradation Induced by Thermal Effect in SOI Power LDMOSFETs Using Accumulation Mode Device Structure By Weitao CHENG, Akinobu TERAMOTO, Tadahiro OHMI	[View] [Download]
Abstract: In this paper, we demonstrate that the advantages of obvious improvement o f the mobility and current drivability at high temperatures and the greatly suppressed self-heating effects in accumulation mode SOI power LDMOSFETs. We reveal the mechanisms of these advantages are resulted from the bulk current and accumulation mode device structure and propose that the accumulation mode device structure is very useful to realize high performance SOI power LDMOSFETs.

	Optimization of the Stray Inductance in Three-Phase MOSFET Power Modules Aided by means of PEEC Simulation By Ole MÃœHLFELD, F.W. FUCHS	[View] [Download]
Abstract: Minimum stray inductances are of high importance for power modules and stacks of converters. This paper describes the optimization of the stray inductance for a compact DBC based three-phase power module for use in 5 to 20 kW converters for automotive application. The inductances of different DBC layouts and mounting technologies are compared and optimized, including chip connection with soldered tapes. The simulated values are compared with measurement results.

	Passive Turn-On Process of IGBTs in Matrix Converter Applications By Roman BABURSKE, Daniel DOMES, Josef LUTZ, Wilfried HOFMANN	[View] [Download]
Abstract: The passive turn-on of IGBTs occurs in Matrix converter applications. This paper analyzes different IGBT-types in terms of passive turn-on. Measurements of passive turn-ons of different IGBT-types are shown and compared with diode turn-ons. The dependency of the turn-on voltage peak on the temperature, the gate resistance and the current is investigated. The results are analyzed by numerical device simulations.

	Performances of MOS-Gated GTO in High Voltage Power Applications By CESARE RONSISVALLE, Annunziata SANSEVERINO, Vicenzo ENEA, Carmine ABBATE, Giovanni BUSATTO	[View] [Download]
Abstract: In this paper we present a comparative study between the characteristics of the MOS-Gated GTO, a new power semiconductor device, and the IGBT having the same n-n+p+ vertical structure. The blocking voltage of the analyzed devices ranges between 1.2kV and 4.5kV. Simulation results show that the MOS-GTO exhibits a much better trade-off between on state and switching characteristics than the IGBT particularly in the range of the high blocking voltages. The excellent performances of the MOS-GTO make it a very promising device for high voltage power applications.

	The Effects of the Stray Elements on the Failure of Parallel Connected IGBTs during Turn-Off By Carmine ABBATE, Giovanni BUSATTO, Francesco IANNUZZO	[View] [Download]
Abstract: The very good performances of IGBT modules in terms of current robustness and thermal overstress can be used on power converters in order to obtain cost and weight reduction. Moreover, in order to develop higher performance devices, it is very important to discover and understand instable failure mechanisms that can occur during IGBT operations. The paper presents an experimental characterization aimed to understand the effects of the stray elements of the connecting circuit on the failure of parallel connected IGBT during turn-off at very high collector current with very low gate resistance. The failure mechanism can be associated to the unequal distribution of the current among the devices whose effects are particularly enhanced by the combination of gate resistance and stray inductance in the emitter circuit. The experimental characterization has been executed by means of a non-destructive tester set-up, in order to reduce the number of required devices.

	Trench isolation technique for Reverse Blocking IGBT using Boron Nitride doping wafers By MIQUEL VELLVEHI, JOSE LUIS GALVEZ, XAVIER PERPINYA, XAVIER JORDA, PHILIPPE GODIGNON, JOSE MILLAN	[View] [Download]
Abstract: A new fabrication process for IGBT devices with reverse blocking capability (RB-IGBT) is presented in this paper. The trench isolation technique which provides the reverse blocking capability has been implemented using solid source as doping technique (Boron doping wafers), resulting in a low-cost process in both starting material and time-consuming aspects. The feasibility of the fabrication technique has been demonstrated with the electrical measurements of the fabricated devices.