| |
LUDMOS transistors optimization on a 0.18m SOI CMOS technology
| [View]
[Download]
|
| Author(s) |
Ignacio CORTES |
| Abstract |
This paper is focused on the design and optimization of power LDMOS transistors with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 µm SOI-CMOS technology. Different LDMOS structures which allow breakdown voltages (VBR) higher than 120 V have been analyzed by means of 2D and 3D TCAD simulations. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is compared in terms of the main static (specific on-state resistance vs breakdown voltage (Ron-sp/VBR) trade-off) and dynamic (Gate-to-Drain charge (Qgd) and Gate charge (Qg) vs Ron trade-off) characteristics. The influence of some drift region design parameters, such as the Poly-gate (LPoly) and STI (LSTI) lengths, are also exhaustively analyzed in this work |
| Download |
| Filename: | 0408-epe2009-full-17365313.pdf |
| Filesize: | 714 KB |
|
| Type |
Members Only |
| Date |
Last modified 2010-01-27 by System |
| |
 |