EPE Association: EPE 2022 - DS2a: Active Devices and Components (Wide Bandgap and other New Materials)

EPE 2022 - DS2a: Active Devices and Components (Wide Bandgap and other New Materials)
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2022 ECCE Europe - Conference > EPE 2022 - Topic 01: Devices, Packaging and System Integration > EPE 2022 - DS2a: Active Devices and Components (Wide Bandgap and other New Materials)

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   A Calorimetric and Electrical Method for Measuring Loss Energies of Half-Bridges
By Jörg HAARER [View]
[Download]

Abstract: For the optimal design of power electronic systems the exact knowledge about the different loss mechanisms of the used semiconductor devices is essential. However, conventional measurement methods based on electrical parameters are facing their limits, as switching speed of modern power devices is steadily increasing enabled by the use of wide bandgap semiconductor materials. For this reason, calorimetric measurement techniques are becoming more and more popular. However, due to the nature of their principle, calorimetric measurement methodologies can usually only determine the total power losses of the device under test. To overcome this disadvantage a methology which combines different calorimetric and electrical measurements to separately determine the switching and conduction energies in a half-bridge with an ohmic-inductive load while maintaining the accuracy of calorimetric measurement methods is developed. In addition, the presented methodology identifies the switching energies of the two different switching transitions within one switching period, depending on the load current as well as the dead time, considering thermal influences. A hardware setup for the presented methology, is realized. Using this test setup, the loss energies of a half-bridge based on silicon carbide MOSFETs are investigated. The resulting measurements are presented and verified by measurements with a power analyzer.

   A Novel Technique for the Suppression of the Displacement Current through Power Module Base-plate Capacitance
By Mahmoud SAEIDI [View]
[Download]

Abstract: The voltage gradient is increased to reduce the switching losses in the wide-bandgap (WBG) semiconductors, which causes the higher power density of the system. Fast rise and fall times during switching of WBG semiconductors result in capacitive non-linearities and displacement currents through power module parasitic capacitances, which needs an appropriate filter design During the switching in the power module, the capacitive current flows through the parasitic capacitance of the power module, which causes the disturbances in the system. This leads to the need for a more oversized filter design, which then increases the overall cost and volume of the system and reduces the efficiency of the system. This paper proposes a novel technique to suppress the capacitive displacement currents without switching speed reduction. The proposed method reduces the volume of the common-mode choke (CMC) and addresses the electromagnetic interference (EMI) and electromagnetic compatibility (EMC) issues. The system was experimentally tested using the commercial 1700 V silicon carbide (SiC) half-bridge power module BSM300D12P2E001 to validate the proposed scheme.

   Active substrate termination of discrete and monolithic bidirectional GaN HEMTs in a T-type inverter
By Carsten KURING [View]
[Download]

Abstract: Monolithically integrated lateral Gallium-nitride bidirectional transistors can achieve symmetric conduction and blocking capability at a reduced on-state resistance compared to their discrete counterparts. An actively switched substrate effectively prevents back-gating effects in normal-ly-off GaN-on-Si bidirectional transistors and enables symmetrical loss-minimized switching and on-state characteristics.

   Analysis and Implementation of Effective Placement of EMC Capacitors for WBG Modules
By Mahmoud SAEIDI [View]
[Download]

Abstract: This paper proposes an optimum placement of the electromagnetic capability (EMC) capacitors for the wide band-gap (WBG) devices (SiC). To minimize electromagnetic interference (EMI), the solution of using EMC capacitors near the power module is proposed. Two different EMC capacitor placement scenarios are examined to show how the displacement current is affected. The suggested method reduces the capacitive displacement current during the high slew rate of the drain-source voltage ($dv/dt$), which then helps to minimize the size and overall cost of the common mode choke (CMC). The proposed methods are simple to construct and easy to implement with a faster switching response. The proposed method is experimentally implemented for a half-bridge SiC power module with the heat sink.

   Automated gate impedance network design for SiC MOSFETs using SPICEsolver interfaced with MATLAB environment
By Pawel KUBULUS [View]
[Download]

Abstract: In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

   Benefits of switching from Si to SiC modules with further converter optimization
By Antxon ARRIZABALAGA [View]
[Download]

Abstract: SiC semiconductors have better characteristics than Si, improving power electronics convertersperformances. A prototype that can switch semiconductor technology without changing any other partof the system is built and tested, showing the efficiency improvements achieved with SiC. Finally, atheoretical system level converter optimization is done applying the experimental results.

   Gate Input Capacitance Characterization for Power MOSFETs Using Turn-on and Turn-off Switching Waveforms
By Yota NISHITANI [View]
[Download]

Abstract: We propose a novel method for characterizing the input capacitance of power metal-oxide semiconductor field-effect transistors (MOSFETs). In contrast with the conventional method, our switching-based characterization extracts gate-source and gate-drain capacitances in a single setup, without partial differentiation. Characterization using both turn-on and turn-off switching waveforms improved the simulation accuracy and reduced the switching timing error by a factor of more than 2.5x.

   Influence of Current Collapse due to Vds Bias Effect on GaN-HEMTs Id-Vds Characteristics in Saturation Region
By Xuyang LU [View]
[Download]

Abstract: A new method is proposed in this paper to investigate the influence of current collapse effect on theId-Vds characteristics of GaN-HEMTs in high voltage region based on a modified H-bridge circuit. Themeasured Id-Vds characteristics with and without the Vds bias are compared, which shows the effect ofcharge trapping due to the Vds bias on device Id-Vds characteristics in saturation region. These data willbe used for a device model including the current collapse effect in full Id-Vds region.

   Investigation of the Static Performance and Avalanche Reliability of High Voltage 4H-SiC Merged-PiN-Schottky Diodes
By Chengjun SHEN [View]
[Download]

Abstract: A comprehensive range of static measurements and UIS tests have been conducted for Silicon PiN diodes, SiC JBS diodes and SiC MPS diodes with temperatures ranging to up to 175°C. The results shows that the forward voltage of Silicon PiN diode is lower at the on-state, even at high temperatures and at high currents. Higher forward voltage and positive temperature coefficient are observed for SiC devices during the static measurements, while they outperform the Silicon devices in terms of the electrothermal ruggedness, as validated by the UIS measurements and its subsequent calculated avalanche energy and die area as measured by means of CT-Scan imaging of the devices.

   Measurement of Coss-V characteristic of the 1.7kV/900A SiC power module and estimation of the channel current
By Jacek RABKOWSKI [View]
[Download]

Abstract: This article presents a novel method for dynamic measurements of COSS-V characteristics of SiC power modules based on the process of charging the output capacitance of the transistors. The technique has been validated for a 1.2kV/450A power module with this characteristic available in its datasheet, showing good compliance. Then, this technique has been used to determine the COSS-V characteristics of a 1.7kV/900A SiC MOSFET module, which allowed the extraction of the capacitive current while switching off the transistor. Finally, the channel current and the share of the capacitive current in the drain current were determined for various switched currents and switching speeds. According to the capacitive charge calculations for several cases, the accuracy of the method is high enough to perform switching loss estimations.

   Simulation Tool for Optimization of Digital Active Gate Drive Sequence Using Genetic Algorithm
By Hajime TAKAYAMA [View]
[Download]

Abstract: We demonstrate a simulation tool to optimize the operation of the digital active gate driver (DAGD) for SiC MOSFETs. The binary nature of DAGD's operating principle makes the genetic algorithm a preferable method. The optimization tool is developed by combining a Python-based program and SPICE simulation. Optimized solutions exhibit improved switching characteristics in wide operating conditions. The effect of conditions on obtained solutions is also analyzed.

   Study on the gate loop design and its impact on switching characteristics of GaN Transistors
By Xiaomeng GENG [View]
[Download]

Abstract: This paper studies design parameters for the gate loop of GaN-based transistors. To achieve stable and fast switching of the GaN transistors aiming at MHz-range operation, different layout factors and their influence on gate loop inductances are investigated in simulations and measurements. Experimental results demonstrating the impact of driver ICs and their packages on the switching characteristics are presented as well.

   Threshold voltage shifting and Junction temperature sensing in GaN HEMTs
By Olayiwola ALATISE [View]
[Download]

Abstract: Junction temperature sensing in GaN HEMTs has been identified as a critical challenge for condition monitoring especially under power cycling conditions. The use of temperature sensitive electrical parameters has been widely studied. In GaN devices, the ON-state resistance and gate leakage currents have been identified as TSEPs as both are junction temperature sensitive. Circuits capable of measuring the gate leakage currents in commercially available GaN HEMTs have previously been presented, however, the impact of variability in the threshold voltage on junction temperature sensing requires further investigation. In this paper, junction temperature measurements are implemented using the gate current as a TSEP and are compared with the junction temperature inferred from the ON-state resistance. The measured junction temperatures were verified against electrothermal simulations using manufacturer provided thermal networks. Threshold shift from charge trapping in Schottky GaN HEMTs has been shown to impact the temperature dependence of the gate leakage currents and ON-state resistance. It is important to account for these changes when using them as temperature sensitive electric parameters for real time junction temperature estimation in GaN HEMTs.

   Turn-on Losses Optimization for Medium Power SiC MOSFET Half-bridge Module
By Pham Ha Trieu TO [View]
[Download]

Abstract: This paper explains the mechanism of the parasitic turn-on (PTO) effect in a medium power SiCMOSFET half-bridge module and the relation between it and the reverse-recovery process ofMOSFET's body diode. Based on that knowledge, a detail practical turn-on losses optimizationprocess for medium power SiC MOSFET modules using PTO is presented. To quantify the stability ofthis method, some quantitative metrics are suggested to measure the critical values' sensitivity. Theexperimental measurements show that turn-on losses can be reduced 50\% lower than conventionaltuning method.

   Verification of GaN-HEMT Spice Models Using an S-parameters Approach
By Alonso GUTIERREZ GALEANO [View]
[Download]

Abstract: This paper describes a complementary S-Parameters approach to verify the Spice model accuracy of power GaNHEMT devices regarding their capacitive and inductive aspects represented in graphic Smith charts. This approach correlates the Smith charts of experimental and simulated results in order to provide insights to improve the model characteristics. The correlation is carried out by processing the experimental results and the Spice simulated data using the Smithplot Python library. dditionally, a complementary study considers the input and output reflection coefficients to stablish a connection between the measured and simulated parameters in frequency and voltage. Possibilities of dissociating both package parasitic elements and intrinsic GaN capacitances confirm the potentialof S-parameters as a powerful tool for model verification and study of power GaN-HEMT devices using a radiofrequency approach.

EPE 2022 - DS2a: Active Devices and Components (Wide Bandgap and other New Materials)
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2022 ECCE Europe - Conference > EPE 2022 - Topic 01: Devices, Packaging and System Integration > EPE 2022 - DS2a: Active Devices and Components (Wide Bandgap and other New Materials)
	[return to parent folder]

	A Calorimetric and Electrical Method for Measuring Loss Energies of Half-Bridges By Jörg HAARER	[View] [Download]
Abstract: For the optimal design of power electronic systems the exact knowledge about the different loss mechanisms of the used semiconductor devices is essential. However, conventional measurement methods based on electrical parameters are facing their limits, as switching speed of modern power devices is steadily increasing enabled by the use of wide bandgap semiconductor materials. For this reason, calorimetric measurement techniques are becoming more and more popular. However, due to the nature of their principle, calorimetric measurement methodologies can usually only determine the total power losses of the device under test. To overcome this disadvantage a methology which combines different calorimetric and electrical measurements to separately determine the switching and conduction energies in a half-bridge with an ohmic-inductive load while maintaining the accuracy of calorimetric measurement methods is developed. In addition, the presented methodology identifies the switching energies of the two different switching transitions within one switching period, depending on the load current as well as the dead time, considering thermal influences. A hardware setup for the presented methology, is realized. Using this test setup, the loss energies of a half-bridge based on silicon carbide MOSFETs are investigated. The resulting measurements are presented and verified by measurements with a power analyzer.

	A Novel Technique for the Suppression of the Displacement Current through Power Module Base-plate Capacitance By Mahmoud SAEIDI	[View] [Download]
Abstract: The voltage gradient is increased to reduce the switching losses in the wide-bandgap (WBG) semiconductors, which causes the higher power density of the system. Fast rise and fall times during switching of WBG semiconductors result in capacitive non-linearities and displacement currents through power module parasitic capacitances, which needs an appropriate filter design During the switching in the power module, the capacitive current flows through the parasitic capacitance of the power module, which causes the disturbances in the system. This leads to the need for a more oversized filter design, which then increases the overall cost and volume of the system and reduces the efficiency of the system. This paper proposes a novel technique to suppress the capacitive displacement currents without switching speed reduction. The proposed method reduces the volume of the common-mode choke (CMC) and addresses the electromagnetic interference (EMI) and electromagnetic compatibility (EMC) issues. The system was experimentally tested using the commercial 1700 V silicon carbide (SiC) half-bridge power module BSM300D12P2E001 to validate the proposed scheme.

	Active substrate termination of discrete and monolithic bidirectional GaN HEMTs in a T-type inverter By Carsten KURING	[View] [Download]
Abstract: Monolithically integrated lateral Gallium-nitride bidirectional transistors can achieve symmetric conduction and blocking capability at a reduced on-state resistance compared to their discrete counterparts. An actively switched substrate effectively prevents back-gating effects in normal-ly-off GaN-on-Si bidirectional transistors and enables symmetrical loss-minimized switching and on-state characteristics.

	Analysis and Implementation of Effective Placement of EMC Capacitors for WBG Modules By Mahmoud SAEIDI	[View] [Download]
Abstract: This paper proposes an optimum placement of the electromagnetic capability (EMC) capacitors for the wide band-gap (WBG) devices (SiC). To minimize electromagnetic interference (EMI), the solution of using EMC capacitors near the power module is proposed. Two different EMC capacitor placement scenarios are examined to show how the displacement current is affected. The suggested method reduces the capacitive displacement current during the high slew rate of the drain-source voltage ($dv/dt$), which then helps to minimize the size and overall cost of the common mode choke (CMC). The proposed methods are simple to construct and easy to implement with a faster switching response. The proposed method is experimentally implemented for a half-bridge SiC power module with the heat sink.

	Automated gate impedance network design for SiC MOSFETs using SPICEsolver interfaced with MATLAB environment By Pawel KUBULUS	[View] [Download]
Abstract: In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment.

	Benefits of switching from Si to SiC modules with further converter optimization By Antxon ARRIZABALAGA	[View] [Download]
Abstract: SiC semiconductors have better characteristics than Si, improving power electronics convertersperformances. A prototype that can switch semiconductor technology without changing any other partof the system is built and tested, showing the efficiency improvements achieved with SiC. Finally, atheoretical system level converter optimization is done applying the experimental results.

	Gate Input Capacitance Characterization for Power MOSFETs Using Turn-on and Turn-off Switching Waveforms By Yota NISHITANI	[View] [Download]
Abstract: We propose a novel method for characterizing the input capacitance of power metal-oxide semiconductor field-effect transistors (MOSFETs). In contrast with the conventional method, our switching-based characterization extracts gate-source and gate-drain capacitances in a single setup, without partial differentiation. Characterization using both turn-on and turn-off switching waveforms improved the simulation accuracy and reduced the switching timing error by a factor of more than 2.5x.

	Influence of Current Collapse due to Vds Bias Effect on GaN-HEMTs Id-Vds Characteristics in Saturation Region By Xuyang LU	[View] [Download]
Abstract: A new method is proposed in this paper to investigate the influence of current collapse effect on theId-Vds characteristics of GaN-HEMTs in high voltage region based on a modified H-bridge circuit. Themeasured Id-Vds characteristics with and without the Vds bias are compared, which shows the effect ofcharge trapping due to the Vds bias on device Id-Vds characteristics in saturation region. These data willbe used for a device model including the current collapse effect in full Id-Vds region.

	Investigation of the Static Performance and Avalanche Reliability of High Voltage 4H-SiC Merged-PiN-Schottky Diodes By Chengjun SHEN	[View] [Download]
Abstract: A comprehensive range of static measurements and UIS tests have been conducted for Silicon PiN diodes, SiC JBS diodes and SiC MPS diodes with temperatures ranging to up to 175°C. The results shows that the forward voltage of Silicon PiN diode is lower at the on-state, even at high temperatures and at high currents. Higher forward voltage and positive temperature coefficient are observed for SiC devices during the static measurements, while they outperform the Silicon devices in terms of the electrothermal ruggedness, as validated by the UIS measurements and its subsequent calculated avalanche energy and die area as measured by means of CT-Scan imaging of the devices.

	Measurement of Coss-V characteristic of the 1.7kV/900A SiC power module and estimation of the channel current By Jacek RABKOWSKI	[View] [Download]
Abstract: This article presents a novel method for dynamic measurements of COSS-V characteristics of SiC power modules based on the process of charging the output capacitance of the transistors. The technique has been validated for a 1.2kV/450A power module with this characteristic available in its datasheet, showing good compliance. Then, this technique has been used to determine the COSS-V characteristics of a 1.7kV/900A SiC MOSFET module, which allowed the extraction of the capacitive current while switching off the transistor. Finally, the channel current and the share of the capacitive current in the drain current were determined for various switched currents and switching speeds. According to the capacitive charge calculations for several cases, the accuracy of the method is high enough to perform switching loss estimations.

	Simulation Tool for Optimization of Digital Active Gate Drive Sequence Using Genetic Algorithm By Hajime TAKAYAMA	[View] [Download]
Abstract: We demonstrate a simulation tool to optimize the operation of the digital active gate driver (DAGD) for SiC MOSFETs. The binary nature of DAGD's operating principle makes the genetic algorithm a preferable method. The optimization tool is developed by combining a Python-based program and SPICE simulation. Optimized solutions exhibit improved switching characteristics in wide operating conditions. The effect of conditions on obtained solutions is also analyzed.

	Study on the gate loop design and its impact on switching characteristics of GaN Transistors By Xiaomeng GENG	[View] [Download]
Abstract: This paper studies design parameters for the gate loop of GaN-based transistors. To achieve stable and fast switching of the GaN transistors aiming at MHz-range operation, different layout factors and their influence on gate loop inductances are investigated in simulations and measurements. Experimental results demonstrating the impact of driver ICs and their packages on the switching characteristics are presented as well.

	Threshold voltage shifting and Junction temperature sensing in GaN HEMTs By Olayiwola ALATISE	[View] [Download]
Abstract: Junction temperature sensing in GaN HEMTs has been identified as a critical challenge for condition monitoring especially under power cycling conditions. The use of temperature sensitive electrical parameters has been widely studied. In GaN devices, the ON-state resistance and gate leakage currents have been identified as TSEPs as both are junction temperature sensitive. Circuits capable of measuring the gate leakage currents in commercially available GaN HEMTs have previously been presented, however, the impact of variability in the threshold voltage on junction temperature sensing requires further investigation. In this paper, junction temperature measurements are implemented using the gate current as a TSEP and are compared with the junction temperature inferred from the ON-state resistance. The measured junction temperatures were verified against electrothermal simulations using manufacturer provided thermal networks. Threshold shift from charge trapping in Schottky GaN HEMTs has been shown to impact the temperature dependence of the gate leakage currents and ON-state resistance. It is important to account for these changes when using them as temperature sensitive electric parameters for real time junction temperature estimation in GaN HEMTs.

	Turn-on Losses Optimization for Medium Power SiC MOSFET Half-bridge Module By Pham Ha Trieu TO	[View] [Download]
Abstract: This paper explains the mechanism of the parasitic turn-on (PTO) effect in a medium power SiCMOSFET half-bridge module and the relation between it and the reverse-recovery process ofMOSFET's body diode. Based on that knowledge, a detail practical turn-on losses optimizationprocess for medium power SiC MOSFET modules using PTO is presented. To quantify the stability ofthis method, some quantitative metrics are suggested to measure the critical values' sensitivity. Theexperimental measurements show that turn-on losses can be reduced 50\% lower than conventionaltuning method.

	Verification of GaN-HEMT Spice Models Using an S-parameters Approach By Alonso GUTIERREZ GALEANO	[View] [Download]
Abstract: This paper describes a complementary S-Parameters approach to verify the Spice model accuracy of power GaNHEMT devices regarding their capacitive and inductive aspects represented in graphic Smith charts. This approach correlates the Smith charts of experimental and simulated results in order to provide insights to improve the model characteristics. The correlation is carried out by processing the experimental results and the Spice simulated data using the Smithplot Python library. dditionally, a complementary study considers the input and output reflection coefficients to stablish a connection between the measured and simulated parameters in frequency and voltage. Possibilities of dissociating both package parasitic elements and intrinsic GaN capacitances confirm the potentialof S-parameters as a powerful tool for model verification and study of power GaN-HEMT devices using a radiofrequency approach.