| Abstract |
In order to ensure proper switching of SiC devices gate impedance has to be carefully selected. Chosen topology and parameter values allow for damping the oscillations in poorly designed layouts, as well as adjusting dV/dt levels in cases where layout allows for too fast switching. Due to a wide choice of gate impedance topologies, some with multiple tunable parameters, experimental fine-tuning is a time-consuming process and analytical predictions do not take full effect of the parasitic elements into account. For this reason, an automated design process is developed using Matlab and LTSpice and the results are verified experimentally in a Double Pulse Test(DPT) setup, for the prediction accuracy assessment. |
