EPE Association: EPE 1997 – 27: Dialogue Session DS1b-2: SWITCHES

EPE 1997 – 27: Dialogue Session DS1b-2: SWITCHES - POWER SEMICONDUCTOR TECHNOLOGY
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1997 - Conference > EPE 1997 – 27: Dialogue Session DS1b-2: SWITCHES - POWER SEMICONDUCTOR TECHNOLOGY

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   ON THE NATURE OF LEAKAGE CURRENT OF FAST RECOVERY SILICON RECTIFIERS
By V. V. N. Obreja; Gh. Dinoiu [View]
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Abstract: Fast recovery silicon rectifiers have at high junction operating temperature, a leakage reverse current significantly higher than similar standard rectifiers. Experimental electrical characteristics for both electron irradiated and gold diffused diodes have been analyzed in comparison with the characteristics of similar standard diodes. A 10 A silicon rectifier diode which is competitive with similar commercial devices available now on the market has been used as test device. It is shown that near the room temperature, fast recovery silicon rectifiers have a reverse leakage current dominated by the junction peripheral surface component and not by the bulk generation component. Towards the maximum junction operating temperature, the reverse current of fast diodes is dominated by the bulk component but a surface component, at least as large as the total reverse current of similar standard diodes is still present. Consequently, fast recovery rectifiers have to operate at a lower junction temperature and reverse voltage in order to be avoided a device failure.

   POWER SDB-DEVICES WITH REGULARLY GROOVED INTERFACES
By I. V. Grckhov; L.S. Kostina; T.S. Argunova; E.D. Kim; S.C. Kim; J.M. Park [View]
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Abstract: A modified Silicon Direct Bonding technology was developed allowing to obtain low dislocation density and void free interfaces in the course of the fabrication of power devices. With a novel technique a contact between smooth and regularly grooved surfaces of silicon wafers was realized. Structural quality of directly bonded surface grooved compositions was revealed. The innovation was based on the fact that, due to dislocation peculiar tendency to move to free surfaces, they can be collected by the inter-facial grooves. The relevant calculations of the dislocation behavior were made. Electrical properties of bonded structures with regularly grooved interfaces were investigated, and suitability of developed technique for semiconductor device manufacturing was demonstrated. Continuously bonded surface grooved diodes, n-p-n bipolar transistors, buried grid gate turn off thyristors and n-p-n-p reverse Switch-on dynistors were fabricated and examined. The design of a buried gate static induction device based on the developed technology was proposed.

   RECOMBINATION LIFETIME DEGRADATION IN THERMALLY STRESSED N-TYPE BULK SILICON WAFER
By A. Cutolo; S. Daliento; A. Irace; P. Spirito; L. Zeni [View]
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Abstract: The effect of thermal stresses on the recombination process in bulk N-type silicon wafers has been investigated by means of a novel contactless technique. Different parameters such as heating and cooling gradients and maximum heating temperature have been studied and a significative reduction of bulk recombination lifetime has been found for high temperatures and steep cooling gradients. Moreover it has been found that slow cooling gradients, in the range of 100°C/h, do not affect the combination process in a relevant way.

   Optical and electrical measurement of bulk recombination lifetime regardless of surface conditions
By Antonello Cutolo; Santolo Daliento; Andrea Irace; Annunziata Sanseverino; Paolo Spirito; Luigi Zeni [View]
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Abstract: In this paper two different techniques for the measurement of recombination lifetime in silicon arc compared. The same bulk silicon sample has been characterized by means of an interferometric contactless method and an electronic measurement technique. Both methods have been capable of detecting the bulk lifetime value regardless the different boundary conditions and the experimental results obtained with the different methods show an excellent agreement.

   OPTIMISATION OF THE REVERSE RECOVERY BEHAVIOUR OF FAST POWER DIODES USING INJECTION EFFICIENCY AND LIFETIME CONTROL TECHNIQUES
By M. T. Rahimo; N. Y. A. Shammas [View]
[Download]

Abstract: In this paper, the effects of the P emitter doping level and depth on the diode reverse recovery behaviour and snappy recovery are investigated. The work has been carried out by means of simulation using the ETH/ise TCAD simulation package. Results have shown that the diode voltage would snap during the recovery phase at higher P emitter doping levels and diffusion depths under the same operating conditions. The forward voltage drop was kept at a constant value by varying the minority carrier lifetime for each set of specifications. From the results obtained, design optimization shows that lower emitter doping levels and depths combined with an increase in the lifetime value will effectively reduce all reverse recovery parameters, with softer recovery characteristics, lower leakage current while maintaining the same forward voltage drop.

   AN EFFICIENT JUNCTION TERMINATION TECHNIQUE: THE BIASED RING STRUCTURE
By C. Mingues; D. Krizaj; G. Charitat [View]
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Abstract: The paper presents analysis of a Biased Ring junction termination structure. This technique is used for efficient improvement of planar pn junction breakdown properties. A major drawback of this technique is a possibility of local reach-through between the rings, increasing the leakage current and the softness of the breakdown characteristics. An optimized design with decaying width and increased distance between the spiral turns (rings) leads to close to ideal breakdown voltage as confirmed by device modeling as well as experimental results. The influence of the ring spacing and surface. charge density on breakdown properties is discussed. Breakdown voltage of a Biased Ring termination has been found insensitive to and even improving at increased oxide charge density.

   POWER MOS TRANSISTORS GATE OXIDE CHARACTERIZATION. LINKED FAILURE RATE
By Jean Roland Coudrin [View]
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Abstract: For some years energy conversion equipment has been made with power MOS transistors. They are easy to implement particularly by voltage control on the gate, and their natural robustness favoured using them at the expense of bipolar transistors. Trondheim The most vulnerable part of a Power MOS is the thin oxide (80 to 110 nm) located below the polysilicon gate. The quality of this oxide (dimensional homogeneity and intrinsic quality) is a significant parameter for evaluating the manufacturer's know-how and product quality. After an overview of the oxide degradation mechanism and different techniques available for making this characterization, this paper shows the results on devices from four manufacturers, using the ramp voltage test. These results make it possible to estimate the defect number by unit area of oxide for each manufacturer and to give the linked failure rate.

EPE 1997 – 27: Dialogue Session DS1b-2: SWITCHES - POWER SEMICONDUCTOR TECHNOLOGY
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1997 - Conference > EPE 1997 – 27: Dialogue Session DS1b-2: SWITCHES - POWER SEMICONDUCTOR TECHNOLOGY
	[return to parent folder]

	ON THE NATURE OF LEAKAGE CURRENT OF FAST RECOVERY SILICON RECTIFIERS By V. V. N. Obreja; Gh. Dinoiu	[View] [Download]
Abstract: Fast recovery silicon rectifiers have at high junction operating temperature, a leakage reverse current significantly higher than similar standard rectifiers. Experimental electrical characteristics for both electron irradiated and gold diffused diodes have been analyzed in comparison with the characteristics of similar standard diodes. A 10 A silicon rectifier diode which is competitive with similar commercial devices available now on the market has been used as test device. It is shown that near the room temperature, fast recovery silicon rectifiers have a reverse leakage current dominated by the junction peripheral surface component and not by the bulk generation component. Towards the maximum junction operating temperature, the reverse current of fast diodes is dominated by the bulk component but a surface component, at least as large as the total reverse current of similar standard diodes is still present. Consequently, fast recovery rectifiers have to operate at a lower junction temperature and reverse voltage in order to be avoided a device failure.

	POWER SDB-DEVICES WITH REGULARLY GROOVED INTERFACES By I. V. Grckhov; L.S. Kostina; T.S. Argunova; E.D. Kim; S.C. Kim; J.M. Park	[View] [Download]
Abstract: A modified Silicon Direct Bonding technology was developed allowing to obtain low dislocation density and void free interfaces in the course of the fabrication of power devices. With a novel technique a contact between smooth and regularly grooved surfaces of silicon wafers was realized. Structural quality of directly bonded surface grooved compositions was revealed. The innovation was based on the fact that, due to dislocation peculiar tendency to move to free surfaces, they can be collected by the inter-facial grooves. The relevant calculations of the dislocation behavior were made. Electrical properties of bonded structures with regularly grooved interfaces were investigated, and suitability of developed technique for semiconductor device manufacturing was demonstrated. Continuously bonded surface grooved diodes, n-p-n bipolar transistors, buried grid gate turn off thyristors and n-p-n-p reverse Switch-on dynistors were fabricated and examined. The design of a buried gate static induction device based on the developed technology was proposed.

	RECOMBINATION LIFETIME DEGRADATION IN THERMALLY STRESSED N-TYPE BULK SILICON WAFER By A. Cutolo; S. Daliento; A. Irace; P. Spirito; L. Zeni	[View] [Download]
Abstract: The effect of thermal stresses on the recombination process in bulk N-type silicon wafers has been investigated by means of a novel contactless technique. Different parameters such as heating and cooling gradients and maximum heating temperature have been studied and a significative reduction of bulk recombination lifetime has been found for high temperatures and steep cooling gradients. Moreover it has been found that slow cooling gradients, in the range of 100°C/h, do not affect the combination process in a relevant way.

	Optical and electrical measurement of bulk recombination lifetime regardless of surface conditions By Antonello Cutolo; Santolo Daliento; Andrea Irace; Annunziata Sanseverino; Paolo Spirito; Luigi Zeni	[View] [Download]
Abstract: In this paper two different techniques for the measurement of recombination lifetime in silicon arc compared. The same bulk silicon sample has been characterized by means of an interferometric contactless method and an electronic measurement technique. Both methods have been capable of detecting the bulk lifetime value regardless the different boundary conditions and the experimental results obtained with the different methods show an excellent agreement.

	OPTIMISATION OF THE REVERSE RECOVERY BEHAVIOUR OF FAST POWER DIODES USING INJECTION EFFICIENCY AND LIFETIME CONTROL TECHNIQUES By M. T. Rahimo; N. Y. A. Shammas	[View] [Download]
Abstract: In this paper, the effects of the P emitter doping level and depth on the diode reverse recovery behaviour and snappy recovery are investigated. The work has been carried out by means of simulation using the ETH/ise TCAD simulation package. Results have shown that the diode voltage would snap during the recovery phase at higher P emitter doping levels and diffusion depths under the same operating conditions. The forward voltage drop was kept at a constant value by varying the minority carrier lifetime for each set of specifications. From the results obtained, design optimization shows that lower emitter doping levels and depths combined with an increase in the lifetime value will effectively reduce all reverse recovery parameters, with softer recovery characteristics, lower leakage current while maintaining the same forward voltage drop.

	AN EFFICIENT JUNCTION TERMINATION TECHNIQUE: THE BIASED RING STRUCTURE By C. Mingues; D. Krizaj; G. Charitat	[View] [Download]
Abstract: The paper presents analysis of a Biased Ring junction termination structure. This technique is used for efficient improvement of planar pn junction breakdown properties. A major drawback of this technique is a possibility of local reach-through between the rings, increasing the leakage current and the softness of the breakdown characteristics. An optimized design with decaying width and increased distance between the spiral turns (rings) leads to close to ideal breakdown voltage as confirmed by device modeling as well as experimental results. The influence of the ring spacing and surface. charge density on breakdown properties is discussed. Breakdown voltage of a Biased Ring termination has been found insensitive to and even improving at increased oxide charge density.

	POWER MOS TRANSISTORS GATE OXIDE CHARACTERIZATION. LINKED FAILURE RATE By Jean Roland Coudrin	[View] [Download]
Abstract: For some years energy conversion equipment has been made with power MOS transistors. They are easy to implement particularly by voltage control on the gate, and their natural robustness favoured using them at the expense of bipolar transistors. Trondheim The most vulnerable part of a Power MOS is the thin oxide (80 to 110 nm) located below the polysilicon gate. The quality of this oxide (dimensional homogeneity and intrinsic quality) is a significant parameter for evaluating the manufacturer's know-how and product quality. After an overview of the oxide degradation mechanism and different techniques available for making this characterization, this paper shows the results on devices from four manufacturers, using the ramp voltage test. These results make it possible to estimate the defect number by unit area of oxide for each manufacturer and to give the linked failure rate.