EPE Association: 02 - Madep - M02 - MATERIAL AND PROCESSES 02

02 - Madep - M02 - MATERIAL AND PROCESSES 02
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1991 - EPE-MADEP Joint Sessions > 02 - Madep - M02 - MATERIAL AND PROCESSES 02

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   RAPID THERMAL EPITAXIAL GROWTH FOR STATIC INDUCTION THYRISTORS
By L. Ye; D. W. McNeill; J. H. Montgomery; S. H. Raza; B. M. Armstrong; H. S. Gamble [View]
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Abstract: A rapid thermal chemical vapour deposition system has been used for the growth of epitaxial silicon layers on silicon substrates at the temperature of 1035°C and pressure of 7mbar. The epitaxial layers are further used to fabricate buried grid static induction thyristors. The results from SIMS and micrograph show that no autodoping occurred during the epitaxial growth and I-V characteristics illustrate that the device operate satisfactorily.

   PROPERTIES OF THE SIPOS-SILICON INTERFACE AND THEIR IMPACT ON THE REVERSE CHARACTERISTIC OF POWER DEVICES
By G. H. Schulze; E. P. Burte [View]
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Abstract: Effective densities of fixed interface charges and of interface traps present at Semi-Insulating POlycrystalline Silicon (SIPOS)-silicon interfaces were evaluated by applying the high frequency capacitance-voltage technique to metal SIPOS-silicon capacitors. Furthermore, mesa-structured high voltage diodes were passivated by SIPOS thin films. Leakage current and breakdown voltage as well as densities of fixed interface charges and of interface traps of the above devices depend on the temperature of an post-deposition annealing process. The experiments reveal a correlation between interface trap density and leakage current on the one hand and fixed interface charge density and breakdown voltage on the other hand. By applying a device simulation program, the breakdown voltage of the high voltage devices investigated was calculated in dependence on the density of fixed interface charges by assuming a insulating passivation film. Experimental and theoretical values of the breakdown voltage agree very well. The relationship between leakage current and interface trap density could also be confirmed by using the above mentioned program.

   INTEGRITY OF THIN OXIDES ON HIGHLY RESISTIVE EPITAXIAL SILICON FOR POWER DEVICES
By T. Brozek; A. Jakubowski; Z.Sawicki [View]
[Download]

Abstract: ln the paper the lntegrity of silicon dioxide, one of the best passivating and lnsulating material, is investigated for the case when the oxide is grown on lightly doped (below 10to13 cm to-3) silicon substrate. Experimental results obtained with the metal-oxide-semiconductor sandwich structure show that the dielectric strength of oxides under investigation is comparable to that of oxides used for other micro-electronic application and reaches 11 MV/cm. It is also shown that as a result of a typical low-temperature annealing an improvement of intrinsic breakdown parameters takes place, but an increase of defect number ln the oxide is simultanously observed.

   THE SIPOS-Si-INTERFACE - A CRITICAL ISSUE FOR POWER DEVICE PASSIVATION
By T. Stockmeier; T. H. Haddon [View]
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Abstract: IV- and CV-curves of Metal-SIPOS-Si-(MSS) - capacitors were simulated and measured. With the assumption that the flow of carriers across the SIPOS-Si-Interface is not affected by an interfacical barrier, an excellent agreement between measurement and simulation was obtained. To confirm this, very thin thermal oxides were grown on silicon before SIPOS deposition to act as a barrier for the current transport. This behaviour could clearly be detected in the IV- and CV-curves. Because the fabrication of the MSS-capacitor was part of the fabrication process of power diodes, a direct correlation of IV- and CV-curves to the blocking characteristics of diodes, passivated by such means, could be made. It was found that already a very thin oxide layer (3.4 nm) between Si and SIPOS, which acts as a barrier for the current transport across the interface, can cause a dramatic reduction of the maximum blocking voltage and a remarkable increase in leakage current.

   STUDY ON THE CONTACT CHARACTERISTICS BETWEEN THE HIGH DOPING SILICON AND METAL
By Li yangping; Xu chuanxiang [View]
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Abstract: The specific contact resistance of electrode of power silicon semiconductor devices has been measured with Shockley's transmission line model method. It is found that the specific contact resistance of Al-Si contact decreases with semiconductor surface doping concentration. And when surface doping concentration is 10to20CM-3, the specific contact resistance of Al-Si contact is about 10to-5 Ohm • CM². These experimental results agree with theoretical calculation obtained from the tunnelling conduction mechanism. For high doping silicon and different metal electrode, it is found that the specific contact resistance depends on the potential barrier height formed by silicon and different metal. The dependence of specific contact resistance on the temperature at which the Al-Si alloy is formed has also been tested and studied in this paper. The relation of the specific contact resistance to the temperature in the range of 400-750°C has been obtained. It is shown that there is an optimum temperature to form Al-Si alloy for different type conduction silicon. Based on these experimental results, an attempt is made to analysis the effect of various factors on the specific contact resistance.

   SILICON DIRECT BONDING FOR POWER DEVICE MANUFACTURE
By C. Parkes; N. S. J. Mitchell; H. S. Gamble; B. M. Armstrong [View]
[Download]

Abstract: A silicon direct bonding technique has been developed allowing cleaning and bonding of silicon wafers without touching their polished surfaces. A bond strength in excess of 100 kg/cm2 was achieved for samples annealed at temperatures of 1200°C. The suitability of the bonding process was determined by the manufacture of various silicon devices. PN junction diodes yielded N-factors of between 1.03-1.2 and high breakdown voltage when junction shifting diffusions were employed. PIN diodes, allowing the depletion region to be scanned across the weld interface, showed that a density of approximately 5x10to11 cm to-2 interface states existed. Common-emitter current gains of up to 400 were achieved for NPN transistors with the bond in the active region of the device showing that although a high density of interface states exist, their effect need not be significant. The manufacture of 8.3mm diameter Gate Turn-off Thyristors proved the viability of the process for larger area devices.

02 - Madep - M02 - MATERIAL AND PROCESSES 02
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1991 - EPE-MADEP Joint Sessions > 02 - Madep - M02 - MATERIAL AND PROCESSES 02
	[return to parent folder]

	RAPID THERMAL EPITAXIAL GROWTH FOR STATIC INDUCTION THYRISTORS By L. Ye; D. W. McNeill; J. H. Montgomery; S. H. Raza; B. M. Armstrong; H. S. Gamble	[View] [Download]
Abstract: A rapid thermal chemical vapour deposition system has been used for the growth of epitaxial silicon layers on silicon substrates at the temperature of 1035°C and pressure of 7mbar. The epitaxial layers are further used to fabricate buried grid static induction thyristors. The results from SIMS and micrograph show that no autodoping occurred during the epitaxial growth and I-V characteristics illustrate that the device operate satisfactorily.

	PROPERTIES OF THE SIPOS-SILICON INTERFACE AND THEIR IMPACT ON THE REVERSE CHARACTERISTIC OF POWER DEVICES By G. H. Schulze; E. P. Burte	[View] [Download]
Abstract: Effective densities of fixed interface charges and of interface traps present at Semi-Insulating POlycrystalline Silicon (SIPOS)-silicon interfaces were evaluated by applying the high frequency capacitance-voltage technique to metal SIPOS-silicon capacitors. Furthermore, mesa-structured high voltage diodes were passivated by SIPOS thin films. Leakage current and breakdown voltage as well as densities of fixed interface charges and of interface traps of the above devices depend on the temperature of an post-deposition annealing process. The experiments reveal a correlation between interface trap density and leakage current on the one hand and fixed interface charge density and breakdown voltage on the other hand. By applying a device simulation program, the breakdown voltage of the high voltage devices investigated was calculated in dependence on the density of fixed interface charges by assuming a insulating passivation film. Experimental and theoretical values of the breakdown voltage agree very well. The relationship between leakage current and interface trap density could also be confirmed by using the above mentioned program.

	INTEGRITY OF THIN OXIDES ON HIGHLY RESISTIVE EPITAXIAL SILICON FOR POWER DEVICES By T. Brozek; A. Jakubowski; Z.Sawicki	[View] [Download]
Abstract: ln the paper the lntegrity of silicon dioxide, one of the best passivating and lnsulating material, is investigated for the case when the oxide is grown on lightly doped (below 10to13 cm to-3) silicon substrate. Experimental results obtained with the metal-oxide-semiconductor sandwich structure show that the dielectric strength of oxides under investigation is comparable to that of oxides used for other micro-electronic application and reaches 11 MV/cm. It is also shown that as a result of a typical low-temperature annealing an improvement of intrinsic breakdown parameters takes place, but an increase of defect number ln the oxide is simultanously observed.

	THE SIPOS-Si-INTERFACE - A CRITICAL ISSUE FOR POWER DEVICE PASSIVATION By T. Stockmeier; T. H. Haddon	[View] [Download]
Abstract: IV- and CV-curves of Metal-SIPOS-Si-(MSS) - capacitors were simulated and measured. With the assumption that the flow of carriers across the SIPOS-Si-Interface is not affected by an interfacical barrier, an excellent agreement between measurement and simulation was obtained. To confirm this, very thin thermal oxides were grown on silicon before SIPOS deposition to act as a barrier for the current transport. This behaviour could clearly be detected in the IV- and CV-curves. Because the fabrication of the MSS-capacitor was part of the fabrication process of power diodes, a direct correlation of IV- and CV-curves to the blocking characteristics of diodes, passivated by such means, could be made. It was found that already a very thin oxide layer (3.4 nm) between Si and SIPOS, which acts as a barrier for the current transport across the interface, can cause a dramatic reduction of the maximum blocking voltage and a remarkable increase in leakage current.

	STUDY ON THE CONTACT CHARACTERISTICS BETWEEN THE HIGH DOPING SILICON AND METAL By Li yangping; Xu chuanxiang	[View] [Download]
Abstract: The specific contact resistance of electrode of power silicon semiconductor devices has been measured with Shockley's transmission line model method. It is found that the specific contact resistance of Al-Si contact decreases with semiconductor surface doping concentration. And when surface doping concentration is 10to20CM-3, the specific contact resistance of Al-Si contact is about 10to-5 Ohm • CM². These experimental results agree with theoretical calculation obtained from the tunnelling conduction mechanism. For high doping silicon and different metal electrode, it is found that the specific contact resistance depends on the potential barrier height formed by silicon and different metal. The dependence of specific contact resistance on the temperature at which the Al-Si alloy is formed has also been tested and studied in this paper. The relation of the specific contact resistance to the temperature in the range of 400-750°C has been obtained. It is shown that there is an optimum temperature to form Al-Si alloy for different type conduction silicon. Based on these experimental results, an attempt is made to analysis the effect of various factors on the specific contact resistance.

	SILICON DIRECT BONDING FOR POWER DEVICE MANUFACTURE By C. Parkes; N. S. J. Mitchell; H. S. Gamble; B. M. Armstrong	[View] [Download]
Abstract: A silicon direct bonding technique has been developed allowing cleaning and bonding of silicon wafers without touching their polished surfaces. A bond strength in excess of 100 kg/cm2 was achieved for samples annealed at temperatures of 1200°C. The suitability of the bonding process was determined by the manufacture of various silicon devices. PN junction diodes yielded N-factors of between 1.03-1.2 and high breakdown voltage when junction shifting diffusions were employed. PIN diodes, allowing the depletion region to be scanned across the weld interface, showed that a density of approximately 5x10to11 cm to-2 interface states existed. Common-emitter current gains of up to 400 were achieved for NPN transistors with the bond in the active region of the device showing that although a high density of interface states exist, their effect need not be significant. The manufacture of 8.3mm diameter Gate Turn-off Thyristors proved the viability of the process for larger area devices.