| Abstract |
IV- and CV-curves of Metal-SIPOS-Si-(MSS) - capacitors were simulated and measured. With the assumption that the flow of carriers across the SIPOS-Si-Interface is not affected by an interfacical barrier, an excellent agreement between measurement and simulation was obtained. To confirm this, very thin thermal oxides were grown on silicon before SIPOS deposition to act as a barrier for the current transport. This behaviour could clearly be detected in the IV- and CV-curves. Because the fabrication of the MSS-capacitor was part of the fabrication process of power diodes, a direct correlation of IV- and CV-curves to the blocking characteristics of diodes, passivated by such means, could be made. It was found that already a very thin oxide layer (3.4 nm) between Si and SIPOS, which acts as a barrier for the current transport across the interface, can cause a dramatic reduction of the maximum blocking voltage and a remarkable increase in leakage current. |
