EPE Association: EPE 1999 - Topic 01d: Monolitic Power Integration

EPE 1999 - Topic 01d: Monolitic Power Integration
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1999 - Conference > EPE 1999 - Topic 01: DEVICES > EPE 1999 - Topic 01d: Monolitic Power Integration

   [return to parent folder]

   A New Lateral DMOSFET Structure with Extremely Reduced On-Resistance and Enhanced Breakdown Voltage
By M. Zitouni; F. Morancho; P. Rossel; H. tranduc; J. Buxo; I. Pagès [View]
[Download]

Abstract: In this paper, a new concept of lateral DMOSFET for Smart Power Integrated Circuits is proposed, in which a vertical trench oxide is used under the gate end in the drift region, and lateral burried oxide is used in the vertical DMOSFET.

   A Novel Overvoltage Protected Logic Level AC Switch Thanks to Functional Integration
By L. Gonthier; J. Mathias; F. Duclos [View]
[Download]

Abstract: Today, static relays must be robust to withstand the a.c. line transients and to allow systems to be compliant with new european ElectroMagnetic Compatibility (EMC) standards. ACSs (for Alternative Current Switches) have been designed in this goal, i.e. to offer more robust semiconductor devices. In other hand, ACSs have been developed in a functional integration approach. They can be used directly between a micro-controller and the load. No external protection or buffer circuit are needed. This reduce considerably the overall electronic board size.

   Monolithic Integration of High Voltage Devices Compatible with a Standard 5-V CMOS Technology
By B. Villard; F. Calmon; C. Gontrand; J. P. Chante; T. Pedron [View]
[Download]

Abstract: We design and optimise high voltage transistors, fully compatible with a standard 5V CMOS technology (55Vfor PMOS and 70Vconcerning NMOS). Introducing a lightly doped and deeply diffused well around the drain in order to increase its breakdown voltage makes the high voltage transistors. Our first task was to create a simulation model for the high voltage transistor, using a bidimensional (2D) numerical process code . A few adjustments were made in order to match the model with reality. Then, we simulated the electrical behaviour of the transistor, using a 2D device simulator. This enabled us to understand some of the physical phenomena related to high voltage and find solutions to improve the electrical characteristics of the device, which are realised indeed. It is a simple and low cost solution, which can be applied to many low voltage technologies.

   New Integrated Device for Units Protection: Circuit-Breaker Structures
By J.-P. Laur; J.-L. Sanchez; P. Austin; J. Jalade; M. Marmouget; M. Breil; M. Roy [View]
[Download]

Abstract: In this paper, new two terminals integrated circuit-breaker structures for electrical units protection are investigated. Based on the functional integration concept, devices are compared thanks to simulations performed with the SABER circuit software tool using specific analytical models. The main electrical characteristics are presented as well as the first experimental results and an example of application is given.

   The Gate-Shifted NMOS FET
By P. Santos; A. P. Casimiro; M. I. Castro Simas; M. Lança [View]
[Download]

Abstract: This work presents a new device, the Gate-Shifted NMOS FET, based on a new drain engineering technique. The GS-NMOS is fully compatible with any standard CMOS technology. With this device, breakdown voltage in the range of 50 Volt and specific ON-resistance in the range of 3m Ohm cm² were attained. A comparative analysis between measured characteristics of this device and the characteristics of other high performance devices already described in the literature is presented. The proposed device proved to be highly suitable for the implementation of very low cost smart power circuits aimed at a large variety of applications.

   Use of a normally-on GTO in a linear mode to commute lower than 1kW powers on 240 V/50Hz
By F. Guitton; D. Magnon [View]
[Download]

Abstract: STMicroelectronics has been developing ASD™ products that are well suited for mains network switching (50Hz). These direct commutations, achieved by a GTO structure, generate a lot of conducted electromagnetic perturbations, which are much higher than standard templates. Two solutions are proposed to reduce these perturbations. The first one consists in acting directly on the gate of the GTO. The second solution consists in controlling the turn off GTO current, by an external circuit. In this case, the GTO is used in a linear mode during the commutation. In spite of an increase of commutation losses, this system operates correctly, and offers interesting prospects for ASD™ applications, regarding the EMC aspect.

EPE 1999 - Topic 01d: Monolitic Power Integration
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1999 - Conference > EPE 1999 - Topic 01: DEVICES > EPE 1999 - Topic 01d: Monolitic Power Integration
	[return to parent folder]

	A New Lateral DMOSFET Structure with Extremely Reduced On-Resistance and Enhanced Breakdown Voltage By M. Zitouni; F. Morancho; P. Rossel; H. tranduc; J. Buxo; I. Pagès	[View] [Download]
Abstract: In this paper, a new concept of lateral DMOSFET for Smart Power Integrated Circuits is proposed, in which a vertical trench oxide is used under the gate end in the drift region, and lateral burried oxide is used in the vertical DMOSFET.

	A Novel Overvoltage Protected Logic Level AC Switch Thanks to Functional Integration By L. Gonthier; J. Mathias; F. Duclos	[View] [Download]
Abstract: Today, static relays must be robust to withstand the a.c. line transients and to allow systems to be compliant with new european ElectroMagnetic Compatibility (EMC) standards. ACSs (for Alternative Current Switches) have been designed in this goal, i.e. to offer more robust semiconductor devices. In other hand, ACSs have been developed in a functional integration approach. They can be used directly between a micro-controller and the load. No external protection or buffer circuit are needed. This reduce considerably the overall electronic board size.

	Monolithic Integration of High Voltage Devices Compatible with a Standard 5-V CMOS Technology By B. Villard; F. Calmon; C. Gontrand; J. P. Chante; T. Pedron	[View] [Download]
Abstract: We design and optimise high voltage transistors, fully compatible with a standard 5V CMOS technology (55Vfor PMOS and 70Vconcerning NMOS). Introducing a lightly doped and deeply diffused well around the drain in order to increase its breakdown voltage makes the high voltage transistors. Our first task was to create a simulation model for the high voltage transistor, using a bidimensional (2D) numerical process code . A few adjustments were made in order to match the model with reality. Then, we simulated the electrical behaviour of the transistor, using a 2D device simulator. This enabled us to understand some of the physical phenomena related to high voltage and find solutions to improve the electrical characteristics of the device, which are realised indeed. It is a simple and low cost solution, which can be applied to many low voltage technologies.

	New Integrated Device for Units Protection: Circuit-Breaker Structures By J.-P. Laur; J.-L. Sanchez; P. Austin; J. Jalade; M. Marmouget; M. Breil; M. Roy	[View] [Download]
Abstract: In this paper, new two terminals integrated circuit-breaker structures for electrical units protection are investigated. Based on the functional integration concept, devices are compared thanks to simulations performed with the SABER circuit software tool using specific analytical models. The main electrical characteristics are presented as well as the first experimental results and an example of application is given.

	The Gate-Shifted NMOS FET By P. Santos; A. P. Casimiro; M. I. Castro Simas; M. Lança	[View] [Download]
Abstract: This work presents a new device, the Gate-Shifted NMOS FET, based on a new drain engineering technique. The GS-NMOS is fully compatible with any standard CMOS technology. With this device, breakdown voltage in the range of 50 Volt and specific ON-resistance in the range of 3m Ohm cm² were attained. A comparative analysis between measured characteristics of this device and the characteristics of other high performance devices already described in the literature is presented. The proposed device proved to be highly suitable for the implementation of very low cost smart power circuits aimed at a large variety of applications.

	Use of a normally-on GTO in a linear mode to commute lower than 1kW powers on 240 V/50Hz By F. Guitton; D. Magnon	[View] [Download]
Abstract: STMicroelectronics has been developing ASD™ products that are well suited for mains network switching (50Hz). These direct commutations, achieved by a GTO structure, generate a lot of conducted electromagnetic perturbations, which are much higher than standard templates. Two solutions are proposed to reduce these perturbations. The first one consists in acting directly on the gate of the GTO. The second solution consists in controlling the turn off GTO current, by an external circuit. In this case, the GTO is used in a linear mode during the commutation. In spite of an increase of commutation losses, this system operates correctly, and offers interesting prospects for ASD™ applications, regarding the EMC aspect.