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The Gate-Shifted NMOS FET
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| Author(s) |
P. Santos; A. P. Casimiro; M. I. Castro Simas; M. Lança |
| Abstract |
This work presents a new device, the Gate-Shifted NMOS FET, based on a new drain engineering technique. The GS-NMOS is fully compatible with any standard CMOS technology. With this device, breakdown voltage in the range of 50 Volt and specific ON-resistance in the range of 3m Ohm cm² were attained. A comparative analysis between measured characteristics of this device and the characteristics of other high performance devices already described in the literature is presented. The proposed device proved to be highly suitable for the implementation of very low cost smart power circuits aimed at a large variety of applications. |
| Download |
| Filename: | EPE1999 - PP00822 - Santos.pdf |
| Filesize: | 1.015 MB |
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| Type |
Members Only |
| Date |
Last modified 2004-03-29 by System |
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