EPE Association: 07 - Madep - M1.3 - MEDIUM POWER DEVICES 02

07 - Madep - M1.3 - MEDIUM POWER DEVICES 02
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1991 - EPE-MADEP Joint Sessions > 07 - Madep - M1.3 - MEDIUM POWER DEVICES 02

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   A METHOD FOR NONDESTRUCTIVE TESTING OF BIPOLAR TRANSISTORS, IGBTS AND MOSFETS
By K. Reinmuth [View]
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Abstract: Traditional bipolar transistors and "modern" devices such as IGBTs and MOSFETs are at risk from second breakdown (SB). In MOSFETs and IGBTs, it is the parasitic bipolar transistor (PST) structures that may switch on under unfavorable operating conditions, and, in so doing, are exposed to the same dangers as bipolar transistors. To examine and better understand these processes, a test unit has been developed for the non-destructive determination of the safe operating area (SOA) of the bipolar structures. At present, devices handling up to 1200 V and 120 A can be tested and disconnected from the load circuit within t < 50 ns.

   COMPARISON OF MOS-GATED BIPOLAR TRANSISTOR STRUCTURES
By J. S. Ajit; B. J. Baliga; S. Tandon; A. Reisman [View]
[Download]

Abstract: Simulation and experimental characteristics of a variety of MOS-gated bipolar transistor structures are compared, and a new monolithic MOS-gated bipolar transistor called the Base-Emitter Switched Transistor (BEST) is presented. The new device features a vertical n-channel MOSFET providing the base drive for a vertical NPN bipolar transistor; a lateral enhancement mode n-channel MOSFET for emitter-switching and a lateral depletion mode p-channel MOSFET for base-switching. Simulation results indicate the superiority of the BEST device compared to a power MOSFET and fast-switching IGBTs. These device structures have been fabricated using a DMOS process and experimental measurements corroborate the simulation results.

   MODELING OF CURRENT SENSING POWER VDMOS DEVICES
By K. Djellabi; H. Tranduc: M. Napieralska; J. P. Berry; P. Rossel [View]
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Abstract: In this paper, the properties of Power MOSFETs with a current sensing function (e.g. SENSEFET. HEXSense,....) are studied. An electrical equivalent circuit compatible with the SPICE IIG6 software is described. This model doesn't result in the straightforward paralleling of two MOSFETs as previously published [1]; instead, it accounts for the modulation of the sensing part On-state resistance by the operating state of the power part. Some of the basic properties of the "current mirror" capability of such integrated structures are considered, e.g., current vs. cell number ratio, the sealing-down effect, the dynamic characteristics. Simulations of switching circuits, and comparisons with experimental results are also presented.

   2D Modeling of High Voltage Bipolar Planar Transistors Using SIPOS Layer and Field Plate as Junction Termination Extentions
By G. Charitat; D. Jaume; A. Peyre-Lavigne; P. Rossel [View]
[Download]

Abstract: A very efficient junction termination technic for high-voltage bipolar transistors is demonstrated. Based on the use of a field plate together with a semi-resistive layer (SIPOS), the complementarity of these two guards is shown: junction curvature electric field effects are reduced by the presence of the field plate and the SIPOS layer reduces the peak electric field at the edge of this field plate. The electrical behaviour of such a structure is established by numerical simulation. Comparison with experimental devices is done and leads to excellent agreement. This technic can be extended to other kind of devices, i.e. diodes and MOST.

   A NOVEL DEVICE STRUCTURE FOR LOW VOLTAGE TRANSIENT PROTECTION
By R. Wilson; H. S. Gamble; A. S. Hudson [View]
[Download]

Abstract: A novel structure based on an amplifying gate thyristor for the protection of sensitive electronic devices against high energy overvoltage transients is presented which can be fabricated inexpensively using a standard four mask planar process. The structure permits control of the turn-on process, and enables a large area of the device to be switched into conduction very rapidly. Turn on times of 1 μsec have been observed. The ON state trigger voltage is determined by the avalanche breakdown voltage of a double diffused n+p diode. Devices with triggering voltages as low as 10 volts and with holding currents up to 1200 mA were produced. Test showed that the protectors yielded excellent repeatability in breakover voltage throughout a typical lifetime of operation. Leakage currents in the OFF state prior to triggering were found to be very small - typically < 10 nA - due primarily to the structure used. 3.2 mm² devices were found to absorb currents up to 107 A on a 10 μsec/1000 μsec exponential current waveform with forward voltages of 5 volts, demonstrating the suitability of such a structure for surge protection.

07 - Madep - M1.3 - MEDIUM POWER DEVICES 02
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1991 - EPE-MADEP Joint Sessions > 07 - Madep - M1.3 - MEDIUM POWER DEVICES 02
	[return to parent folder]

	A METHOD FOR NONDESTRUCTIVE TESTING OF BIPOLAR TRANSISTORS, IGBTS AND MOSFETS By K. Reinmuth	[View] [Download]
Abstract: Traditional bipolar transistors and "modern" devices such as IGBTs and MOSFETs are at risk from second breakdown (SB). In MOSFETs and IGBTs, it is the parasitic bipolar transistor (PST) structures that may switch on under unfavorable operating conditions, and, in so doing, are exposed to the same dangers as bipolar transistors. To examine and better understand these processes, a test unit has been developed for the non-destructive determination of the safe operating area (SOA) of the bipolar structures. At present, devices handling up to 1200 V and 120 A can be tested and disconnected from the load circuit within t < 50 ns.

	COMPARISON OF MOS-GATED BIPOLAR TRANSISTOR STRUCTURES By J. S. Ajit; B. J. Baliga; S. Tandon; A. Reisman	[View] [Download]
Abstract: Simulation and experimental characteristics of a variety of MOS-gated bipolar transistor structures are compared, and a new monolithic MOS-gated bipolar transistor called the Base-Emitter Switched Transistor (BEST) is presented. The new device features a vertical n-channel MOSFET providing the base drive for a vertical NPN bipolar transistor; a lateral enhancement mode n-channel MOSFET for emitter-switching and a lateral depletion mode p-channel MOSFET for base-switching. Simulation results indicate the superiority of the BEST device compared to a power MOSFET and fast-switching IGBTs. These device structures have been fabricated using a DMOS process and experimental measurements corroborate the simulation results.

	MODELING OF CURRENT SENSING POWER VDMOS DEVICES By K. Djellabi; H. Tranduc: M. Napieralska; J. P. Berry; P. Rossel	[View] [Download]
Abstract: In this paper, the properties of Power MOSFETs with a current sensing function (e.g. SENSEFET. HEXSense,....) are studied. An electrical equivalent circuit compatible with the SPICE IIG6 software is described. This model doesn't result in the straightforward paralleling of two MOSFETs as previously published [1]; instead, it accounts for the modulation of the sensing part On-state resistance by the operating state of the power part. Some of the basic properties of the "current mirror" capability of such integrated structures are considered, e.g., current vs. cell number ratio, the sealing-down effect, the dynamic characteristics. Simulations of switching circuits, and comparisons with experimental results are also presented.

	2D Modeling of High Voltage Bipolar Planar Transistors Using SIPOS Layer and Field Plate as Junction Termination Extentions By G. Charitat; D. Jaume; A. Peyre-Lavigne; P. Rossel	[View] [Download]
Abstract: A very efficient junction termination technic for high-voltage bipolar transistors is demonstrated. Based on the use of a field plate together with a semi-resistive layer (SIPOS), the complementarity of these two guards is shown: junction curvature electric field effects are reduced by the presence of the field plate and the SIPOS layer reduces the peak electric field at the edge of this field plate. The electrical behaviour of such a structure is established by numerical simulation. Comparison with experimental devices is done and leads to excellent agreement. This technic can be extended to other kind of devices, i.e. diodes and MOST.

	A NOVEL DEVICE STRUCTURE FOR LOW VOLTAGE TRANSIENT PROTECTION By R. Wilson; H. S. Gamble; A. S. Hudson	[View] [Download]
Abstract: A novel structure based on an amplifying gate thyristor for the protection of sensitive electronic devices against high energy overvoltage transients is presented which can be fabricated inexpensively using a standard four mask planar process. The structure permits control of the turn-on process, and enables a large area of the device to be switched into conduction very rapidly. Turn on times of 1 μsec have been observed. The ON state trigger voltage is determined by the avalanche breakdown voltage of a double diffused n+p diode. Devices with triggering voltages as low as 10 volts and with holding currents up to 1200 mA were produced. Test showed that the protectors yielded excellent repeatability in breakover voltage throughout a typical lifetime of operation. Leakage currents in the OFF state prior to triggering were found to be very small - typically < 10 nA - due primarily to the structure used. 3.2 mm² devices were found to absorb currents up to 107 A on a 10 μsec/1000 μsec exponential current waveform with forward voltages of 5 volts, demonstrating the suitability of such a structure for surge protection.