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2D Modeling of High Voltage Bipolar Planar Transistors Using SIPOS Layer and Field Plate as Junction Termination Extentions
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| Author(s) |
G. Charitat; D. Jaume; A. Peyre-Lavigne; P. Rossel |
| Abstract |
A very efficient junction termination technic for high-voltage bipolar transistors is demonstrated. Based on the use of a field plate together with a semi-resistive layer (SIPOS), the complementarity of these two guards is shown: junction curvature electric field effects are reduced by the presence of the field plate and the SIPOS layer reduces the peak electric field at the edge of this field plate. The electrical behaviour of such a structure is established by numerical simulation. Comparison with experimental devices is done and leads to excellent agreement. This technic can be extended to other kind of devices, i.e. diodes and MOST. |
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| Filename: | Unnamed file |
| Filesize: | 3.978 MB |
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| Type |
Members Only |
| Date |
Last modified 2019-06-11 by System |
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