EPE Association: EPE 1993 - 43 - Dialogue Session DS3.1: DEVICES: GTO's, SIT's, IGBT's, DIO's

EPE 1993 - 43 - Dialogue Session DS3.1: DEVICES: GTO's, SIT's, IGBT's, DIO's
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1993 - Conference > EPE 1993 - 43 - Dialogue Session DS3.1: DEVICES: GTO's, SIT's, IGBT's, DIO's

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   LOW SWITCHING LOSS FOUR ELECTRODE GTO THYRISTOR
By J. Arnould; D. Lafore [View]
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Abstract: In view of improving switching performance of GTO Thyristor a four electrode device - cathode, anode, two gates - is developed and investigated. Structure specific features:
- all planar technology
- finely interdigited cathode (40 or 100 "microns" finger widths)
- anode gate available on anode side (same pattem as gate cathode side one)
- vertical profil: assymetric or not
- switching capability 80 A 1000 V
It is shown an improvement of at least a factor 2 in terms of switch off loss. A brief process description is given and a complete circuit equipment described. Experimental results are presented and discussed.

   AN OPTICALLY ACTIVATED SIT FOR HIGH VOLTAGE APPLICATIONS
By K. I. Nuttall; W. Chen [View]
[Download]

Abstract: A twin grid Bipolar Mode SIT structure is proposed for use as an optically activated transistor with normally off electrical characteristics. The introduction of a second grid allows advantage to be taken of the high current gains obtainable from the SIT to produce a structure that combines high responsivity with a high blocking voltage capability. Computer simulation results are presented to indicate the capabilities of the device and the consequences of certain design changes are investigated.

   DESIGN COSIDERATIONS FOR FAST SOFT REVERSE RECOVERY DIODES
By V. Benda [View]
[Download]

Abstract: Both static and dynamic characteristics of power diodes are effected by carrier lifetime, thickness and resistivity of the base region, doping profiles, etc. This paper presents results of the reverse recovery process simulation considering effects of carrier lifetime gradient and P-emitter concentration on the reverse recovery characteristics. For simulation, a model considering one-dimensional P+NN+ diode structure with assumed non-uniform carrier lifetime distribution has been used. The results of computations have been discussed from the viewpoint of parameter improvement of both P+NN+ diodes and integrated diode structures of SPEED type or MSP type with particular emphasis on soft recovery.

   BREAKDOWN VOLTAGE OF ELLIPTIC PN JUNCTIONS
By D. Krizaj; S. Amon [View]
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Abstract: 2-D simulations of diffused profiles reveal that the shapes of curvature regions of PN junctions fit closer to elliptical than cylindrical ones. In this article the investigation into breakdown voltages of diffused PN junctions with different lateral to vertical diffusion depths is presented. Metallurgical junctions of real 2-D diffused PN structures were approximated by elliptic junction curvature. It is shown that breakdown voltages of planar junctions are underestimated if they are calculated as breakdown voltage of a cylindrical junction with junction depth equal to lateral junction depth. The difference between the breakdown voltage of an elliptic and a cylindric junction curvature at lateral to vertical diffusion depth ratio 0.5 can be as large as 25%. Breakdown voltages are more sensitive to junction curvature at larger junction depths and lower substrate concentrations. A set of design curves is given that allows accurate and simple determination of breakdown voltages for substrate dopings from 1013 cm-3 to 1016 cm-3 and junction curvature ratios from 0.5 to 1.

   ANALYSIS OF LATCH-UP EFFECT IN INSULATED GATE BIPOLAR TRANSISTORS
By V .A .Kuzmin; S. N. Yurkov [View]
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Abstract: The paper presents an analytical model of the latch-up effect in insulated gate bipolar transistors (IGBT). The model is based on an equation that describes the voltage distribution along the n+ -p emitter junction of the parasitic thyristor. Expressions describing latch-up current ILT and its dependence upon geometrical and electrophysical parameters of the devices with various topologies are derived. It is shown that ILT-1 is proportional to the sheet resistance of the p-base of the parasitic thyristor and gain factor of the p-n-p transistor. ILT decreases if under-gate region width and especially n + -emitter width increase. The derived formulas determine the temperature dependence of ILT. Obtained results are in good agreement with the available published data.

   SECOND BREAKDOWN AND LATCH-UP BEHAVIOR OF IGBTs
By K. Heumann; M. Quenum [View]
[Download]

Abstract: The semiconductor structure of bipolar transistors can cause failures by second breakdown. Also power MOSFETs and new semiconductor devices like IGBTs with a parasitic npn-structure may be damaged by this mechanism. First generation IGBT with a parasitic thyristor inside the device are additionally contagious for the phenomenum of latch-up. Advances in technology improved the device characteristics. Modern IGBTs seem to be insusceptible for latch-up despite the still existing parasitic thyristor in their structure. This paper gives a short discussion of latch-up and second breakdown phenomena. IGBT of different semiconductor generations during latch-up under various conditions were investigated. A test circuit for these measurements is proposed.

EPE 1993 - 43 - Dialogue Session DS3.1: DEVICES: GTO's, SIT's, IGBT's, DIO's
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1993 - Conference > EPE 1993 - 43 - Dialogue Session DS3.1: DEVICES: GTO's, SIT's, IGBT's, DIO's
	[return to parent folder]

	LOW SWITCHING LOSS FOUR ELECTRODE GTO THYRISTOR By J. Arnould; D. Lafore	[View] [Download]
Abstract: In view of improving switching performance of GTO Thyristor a four electrode device - cathode, anode, two gates - is developed and investigated. Structure specific features: - all planar technology - finely interdigited cathode (40 or 100 "microns" finger widths) - anode gate available on anode side (same pattem as gate cathode side one) - vertical profil: assymetric or not - switching capability 80 A 1000 V It is shown an improvement of at least a factor 2 in terms of switch off loss. A brief process description is given and a complete circuit equipment described. Experimental results are presented and discussed.

	AN OPTICALLY ACTIVATED SIT FOR HIGH VOLTAGE APPLICATIONS By K. I. Nuttall; W. Chen	[View] [Download]
Abstract: A twin grid Bipolar Mode SIT structure is proposed for use as an optically activated transistor with normally off electrical characteristics. The introduction of a second grid allows advantage to be taken of the high current gains obtainable from the SIT to produce a structure that combines high responsivity with a high blocking voltage capability. Computer simulation results are presented to indicate the capabilities of the device and the consequences of certain design changes are investigated.

	DESIGN COSIDERATIONS FOR FAST SOFT REVERSE RECOVERY DIODES By V. Benda	[View] [Download]
Abstract: Both static and dynamic characteristics of power diodes are effected by carrier lifetime, thickness and resistivity of the base region, doping profiles, etc. This paper presents results of the reverse recovery process simulation considering effects of carrier lifetime gradient and P-emitter concentration on the reverse recovery characteristics. For simulation, a model considering one-dimensional P+NN+ diode structure with assumed non-uniform carrier lifetime distribution has been used. The results of computations have been discussed from the viewpoint of parameter improvement of both P+NN+ diodes and integrated diode structures of SPEED type or MSP type with particular emphasis on soft recovery.

	BREAKDOWN VOLTAGE OF ELLIPTIC PN JUNCTIONS By D. Krizaj; S. Amon	[View] [Download]
Abstract: 2-D simulations of diffused profiles reveal that the shapes of curvature regions of PN junctions fit closer to elliptical than cylindrical ones. In this article the investigation into breakdown voltages of diffused PN junctions with different lateral to vertical diffusion depths is presented. Metallurgical junctions of real 2-D diffused PN structures were approximated by elliptic junction curvature. It is shown that breakdown voltages of planar junctions are underestimated if they are calculated as breakdown voltage of a cylindrical junction with junction depth equal to lateral junction depth. The difference between the breakdown voltage of an elliptic and a cylindric junction curvature at lateral to vertical diffusion depth ratio 0.5 can be as large as 25%. Breakdown voltages are more sensitive to junction curvature at larger junction depths and lower substrate concentrations. A set of design curves is given that allows accurate and simple determination of breakdown voltages for substrate dopings from 1013 cm-3 to 1016 cm-3 and junction curvature ratios from 0.5 to 1.

	ANALYSIS OF LATCH-UP EFFECT IN INSULATED GATE BIPOLAR TRANSISTORS By V .A .Kuzmin; S. N. Yurkov	[View] [Download]
Abstract: The paper presents an analytical model of the latch-up effect in insulated gate bipolar transistors (IGBT). The model is based on an equation that describes the voltage distribution along the n+ -p emitter junction of the parasitic thyristor. Expressions describing latch-up current ILT and its dependence upon geometrical and electrophysical parameters of the devices with various topologies are derived. It is shown that ILT-1 is proportional to the sheet resistance of the p-base of the parasitic thyristor and gain factor of the p-n-p transistor. ILT decreases if under-gate region width and especially n + -emitter width increase. The derived formulas determine the temperature dependence of ILT. Obtained results are in good agreement with the available published data.

	SECOND BREAKDOWN AND LATCH-UP BEHAVIOR OF IGBTs By K. Heumann; M. Quenum	[View] [Download]
Abstract: The semiconductor structure of bipolar transistors can cause failures by second breakdown. Also power MOSFETs and new semiconductor devices like IGBTs with a parasitic npn-structure may be damaged by this mechanism. First generation IGBT with a parasitic thyristor inside the device are additionally contagious for the phenomenum of latch-up. Advances in technology improved the device characteristics. Modern IGBTs seem to be insusceptible for latch-up despite the still existing parasitic thyristor in their structure. This paper gives a short discussion of latch-up and second breakdown phenomena. IGBT of different semiconductor generations during latch-up under various conditions were investigated. A test circuit for these measurements is proposed.