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ANALYSIS OF LATCH-UP EFFECT IN INSULATED GATE BIPOLAR TRANSISTORS
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| Author(s) |
V .A .Kuzmin; S. N. Yurkov |
| Abstract |
The paper presents an analytical model of the latch-up effect in insulated gate bipolar transistors (IGBT). The model is based on an equation that describes the voltage distribution along the n+ -p emitter junction of the parasitic thyristor. Expressions describing latch-up current ILT and its dependence upon geometrical and electrophysical parameters of the devices with various topologies are derived. It is shown that ILT-1 is proportional to the sheet resistance of the p-base of the parasitic thyristor and gain factor of the p-n-p transistor. ILT decreases if under-gate region width and especially n + -emitter width increase. The derived formulas determine the temperature dependence of ILT. Obtained results are in good agreement with the available published data. |
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| Filename: | Unnamed file |
| Filesize: | 1.897 MB |
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| Type |
Members Only |
| Date |
Last modified 2019-05-22 by System |
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