EPE Association: EPE 2025 - LS2d: Reliability & Systems & Packaging

EPE 2025 - LS2d: Reliability & Systems & Packaging
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2025 - Conference > EPE 2025 - Topic 07: Semiconductor Devices and Packaging > EPE 2025 - LS2d: Reliability & Systems & Packaging

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   Good practices to sort 650 V GaN die inside a PCB
By Alonso GUTIERREZ GALEANO, Laurent GUILLOT, Pierre-Yves HAMELIN, Emmanuel MARCAULT, Marc ORSATELLI, Antoine IZOULET, Mathieu GAVELLE, Aymeric LAGADEC [View]
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Abstract: This work studies the embedding of 650V d-mode GaN within a PCB using double-side microvias. The study begins with a comparison of electrical parameters before and after packaging in a sample of devices. This comparison aims to evaluate the packaging impact. After, all packaged devices are characterized and statistically classified. This classification allows detecting some parts with atypical values. X-ray tomography on these atypical parts highlight backside die delamination or voids on them. However, this failure detection method could be time-consuming. Therefore, this study proposes a method based on S-parameters for early failure detection. S-parameters analysis and test results on the identified backside delaminated devices reveal their tendency to have higher intrinsic capacitance. Finally, lessons learned through this study have led to propose some guidelines to improve the embedded PCB process for better sort practices.

   Low inductance power module optimized for Flying Capacitor Topology
By Philippe LASSERRE, Cyrille DUCHESNE, Anusha GOPISHETTI [View]
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Abstract: In Renewable Energy domain, power converter require adapted solutions to increase electrothermal performances. In this paper, a high-performance packaging architecture is proposed, dedicated to a flying capacitor topology. Based on 750V SiC bare dies, interconnection technologies, materials and optimized design was established to obtain a dedicated power module, with the support of finite element modeling. A specific assembly process was developed with innovative tooling and was tested at the end of process by electrical static tests and Xray analysis. Power electrical performances was measured by double pulse test method. Electrical characterization and module simulation recovered the value of inductance close to 6nH. Next step is to evaluate the robustness of this new power module with campaigns of passive temperature cycling and power cycling to be performed.

   Power Cycling Reliability of Paralleled IGBT Chips Heated with Conduction and Switching Losses
By James ABUOGO, Josef LUTZ, Thomas BASLER [View]
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Abstract: The results of a power cycling test (PCT) of switches in a commercially available baseplate-less IGBT module with two paralleled chips are presented. The thermal imbalance between the two paralleled chips caused by direct bonded copper (DBC) substrate layout design was found to be the most influencing factor for lifetime of these switches. A modification of the DBC layout is suggested to homogenize thermal loading of the paralleled chips.

EPE 2025 - LS2d: Reliability & Systems & Packaging
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2025 - Conference > EPE 2025 - Topic 07: Semiconductor Devices and Packaging > EPE 2025 - LS2d: Reliability & Systems & Packaging
	[return to parent folder]

	Good practices to sort 650 V GaN die inside a PCB By Alonso GUTIERREZ GALEANO, Laurent GUILLOT, Pierre-Yves HAMELIN, Emmanuel MARCAULT, Marc ORSATELLI, Antoine IZOULET, Mathieu GAVELLE, Aymeric LAGADEC	[View] [Download]
Abstract: This work studies the embedding of 650V d-mode GaN within a PCB using double-side microvias. The study begins with a comparison of electrical parameters before and after packaging in a sample of devices. This comparison aims to evaluate the packaging impact. After, all packaged devices are characterized and statistically classified. This classification allows detecting some parts with atypical values. X-ray tomography on these atypical parts highlight backside die delamination or voids on them. However, this failure detection method could be time-consuming. Therefore, this study proposes a method based on S-parameters for early failure detection. S-parameters analysis and test results on the identified backside delaminated devices reveal their tendency to have higher intrinsic capacitance. Finally, lessons learned through this study have led to propose some guidelines to improve the embedded PCB process for better sort practices.

	Low inductance power module optimized for Flying Capacitor Topology By Philippe LASSERRE, Cyrille DUCHESNE, Anusha GOPISHETTI	[View] [Download]
Abstract: In Renewable Energy domain, power converter require adapted solutions to increase electrothermal performances. In this paper, a high-performance packaging architecture is proposed, dedicated to a flying capacitor topology. Based on 750V SiC bare dies, interconnection technologies, materials and optimized design was established to obtain a dedicated power module, with the support of finite element modeling. A specific assembly process was developed with innovative tooling and was tested at the end of process by electrical static tests and Xray analysis. Power electrical performances was measured by double pulse test method. Electrical characterization and module simulation recovered the value of inductance close to 6nH. Next step is to evaluate the robustness of this new power module with campaigns of passive temperature cycling and power cycling to be performed.

	Power Cycling Reliability of Paralleled IGBT Chips Heated with Conduction and Switching Losses By James ABUOGO, Josef LUTZ, Thomas BASLER	[View] [Download]
Abstract: The results of a power cycling test (PCT) of switches in a commercially available baseplate-less IGBT module with two paralleled chips are presented. The thermal imbalance between the two paralleled chips caused by direct bonded copper (DBC) substrate layout design was found to be the most influencing factor for lifetime of these switches. A modification of the DBC layout is suggested to homogenize thermal loading of the paralleled chips.