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Good practices to sort 650 V GaN die inside a PCB
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| Author(s) |
Alonso GUTIERREZ GALEANO, Laurent GUILLOT, Pierre-Yves HAMELIN, Emmanuel MARCAULT, Marc ORSATELLI, Antoine IZOULET, Mathieu GAVELLE, Aymeric LAGADEC |
| Abstract |
This work studies the embedding of 650V d-mode GaN within a PCB using double-side microvias. The study begins with a comparison of electrical parameters before and after packaging in a sample of devices. This comparison aims to evaluate the packaging impact. After, all packaged devices are characterized and statistically classified. This classification allows detecting some parts with atypical values. X-ray tomography on these atypical parts highlight backside die delamination or voids on them. However, this failure detection method could be time-consuming. Therefore, this study proposes a method based on S-parameters for early failure detection. S-parameters analysis and test results on the identified backside delaminated devices reveal their tendency to have higher intrinsic capacitance. Finally, lessons learned through this study have led to propose some guidelines to improve the embedded PCB process for better sort practices. |
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| Filename: | 0059-epe2025-full-14101969.pdf |
| Filesize: | 1.593 MB |
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| Type |
Members Only |
| Date |
Last modified 2025-08-31 by System |
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