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Power Cycling Reliability of Paralleled IGBT Chips Heated with Conduction and Switching Losses
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| Author(s) |
James ABUOGO, Josef LUTZ, Thomas BASLER |
| Abstract |
The results of a power cycling test (PCT) of switches in a commercially available baseplate-less IGBT module with two paralleled chips are presented. The thermal imbalance between the two paralleled chips caused by direct bonded copper (DBC) substrate layout design was found to be the most influencing factor for lifetime of these switches. A modification of the DBC layout is suggested to homogenize thermal loading of the paralleled chips. |
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| Filename: | 0063-epe2025-full-12321046.pdf |
| Filesize: | 1.934 MB |
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| Type |
Members Only |
| Date |
Last modified 2025-08-31 by System |
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