EPE Association: NORpie 2002 - Topic 07: NEW DEVICES

NORpie 2002 - Topic 07: NEW DEVICES
You are here: EPE Documents > 05 - EPE Supported Conference Proceedings > NORpie - Proceedings > NORpie 2002 > NORpie 2002 - Topic 07: NEW DEVICES

   [return to parent folder]

   Static and Dynamic Characteristics of Junction Field Effect Transistors in 4H Silicon Carbide
By S.-M. Koo; M. Domeij; C-M. Zetterling; M. Östling [View]
[Download]

Abstract: Junction field-effect transistors (JFETs) with a bureid gate have been fabricated in 4H polytype silicon carbide (SiC). The devices show drain currents of ~30-50 mA at room temperature for a channel width of 0.1 mm and turn-off gate voltage of ~20-70 V, depending on the channel thickness. The dc static characteristics were measured up to 300° C, with well-saturated drain currents and a reduction of the current down to 30% of room temperature values. The dynamic characteristics of 4H-SiC JFETs in a circuit with inductive load have also been characterized and discussed.

   Design of a Gate Drive Circuit for Use with SiC JFETs
By B. Allebrand; H-P. Nee [View]
[Download]

Abstract: This paper describes how a gate drive can be designed for use with SiC JFETs. The gate drive is supposed to be used in an experimental set-up, which means that the design is not adapted to production constraints. The gate drive circuit can be devided in four parts: power stage, negative voltage protection, short-circuit protection, and logic unit, which all are described.

   Modelling of High Voltage SiC Bipolar Transistors for Switch Applications
By E. Danielsson; M. Domeij; C-M. Zetterling; M. Östling [View]
[Download]

Abstract: SiC bipolar transistors have been modeled using measurements, device simulations and theoretical calculations from device physics. The model can be used to predict the performance of SiC BJTs in more complex systems, e.g. high voltage integrated circuits. Here the model was used to compare simulation and measurement for switching of inductive load.

   Minimizing Oscillations in the Diode-Less SiC JFET Inverter Bridge
By B. Allebrand; H-P. Nee [View]
[Download]

Abstract: This article describes how the oscillations in the Diode-less SiC JFET Inverter Bridge can be minimized. Different ways of minimizing the oscillations are investigated and simulation results are presented showing how therse oscillations are reduced. The cause of the oscillations are given a thorough review.

NORpie 2002 - Topic 07: NEW DEVICES
You are here: EPE Documents > 05 - EPE Supported Conference Proceedings > NORpie - Proceedings > NORpie 2002 > NORpie 2002 - Topic 07: NEW DEVICES
	[return to parent folder]

	Static and Dynamic Characteristics of Junction Field Effect Transistors in 4H Silicon Carbide By S.-M. Koo; M. Domeij; C-M. Zetterling; M. Östling	[View] [Download]
Abstract: Junction field-effect transistors (JFETs) with a bureid gate have been fabricated in 4H polytype silicon carbide (SiC). The devices show drain currents of ~30-50 mA at room temperature for a channel width of 0.1 mm and turn-off gate voltage of ~20-70 V, depending on the channel thickness. The dc static characteristics were measured up to 300° C, with well-saturated drain currents and a reduction of the current down to 30% of room temperature values. The dynamic characteristics of 4H-SiC JFETs in a circuit with inductive load have also been characterized and discussed.

	Design of a Gate Drive Circuit for Use with SiC JFETs By B. Allebrand; H-P. Nee	[View] [Download]
Abstract: This paper describes how a gate drive can be designed for use with SiC JFETs. The gate drive is supposed to be used in an experimental set-up, which means that the design is not adapted to production constraints. The gate drive circuit can be devided in four parts: power stage, negative voltage protection, short-circuit protection, and logic unit, which all are described.

	Modelling of High Voltage SiC Bipolar Transistors for Switch Applications By E. Danielsson; M. Domeij; C-M. Zetterling; M. Östling	[View] [Download]
Abstract: SiC bipolar transistors have been modeled using measurements, device simulations and theoretical calculations from device physics. The model can be used to predict the performance of SiC BJTs in more complex systems, e.g. high voltage integrated circuits. Here the model was used to compare simulation and measurement for switching of inductive load.

	Minimizing Oscillations in the Diode-Less SiC JFET Inverter Bridge By B. Allebrand; H-P. Nee	[View] [Download]
Abstract: This article describes how the oscillations in the Diode-less SiC JFET Inverter Bridge can be minimized. Different ways of minimizing the oscillations are investigated and simulation results are presented showing how therse oscillations are reduced. The cause of the oscillations are given a thorough review.