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| Filesize: | 289.2 KB |
| Design of a Gate Drive Circuit for Use with SiC JFETs | ||||||
| Author(s) | B. Allebrand; H-P. Nee | |||||
| Abstract | This paper describes how a gate drive can be designed for use with SiC JFETs. The gate drive is supposed to be used in an experimental set-up, which means that the design is not adapted to production constraints. The gate drive circuit can be devided in four parts: power stage, negative voltage protection, short-circuit protection, and logic unit, which all are described. | |||||
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| Type | Members Only | |||||
| Date | Last modified 2006-02-24 by System | |||||
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