EPE 2025 - DS1l: Integration and Packaging | ||
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![]() | A method for detecting the start of delamination at the corners of solder joint in a 3D PCB Integration Assembly of MOSFET SiC
By Souhila BOUZERD, Laurent DUPONT | |
Abstract: The article discusses a method for evaluating the delamination initiation at solder joint corners in a 3D assembly of SiC MOSFETs integrated into a PCB substrate to design a half bridge. This assembly leads to soldering two metallic materials and addresses the integration of small active chips with larger heat-sinks. This technological development is part of the perspective of evaluating the robustness of a new assembly model for wide band Gap components. This assembly consists of metallic base-plate corresponding to the heat-sink soldered on the copper foil of a PCB substrate. Conventional methods fail to detect delamination initiation effectively due to the optimized commutation cell design. Finite element simulations are carried out to assess the sensitivity of another method. Then, prototypes with controlled delamination rate are developed. The results demonstrate that electrical method is sensitive to detect the low delimitation rates comparing to thermal method.
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![]() | Effects of Removing Bottom-side Copper in Baseplate-less Power Modules
By Nikolaj KRISTENSEN, Jakob IVERSEN DEICHGRAEBER, Kerim BRACKOVIC, Szymon BECZKOWSKI, Stig MUNK-NIELSEN, Asger BJØRN JØRGENSEN | |
Abstract: Performance of SiC MOSFETs are limited by theinherent parasitic elements originating from thepackaging structure. In this paper, the parasiticcapacitance of a 1.2 kV SiC MOSFET half-bridgepower module is significantly reduced by removingthe bottom-side copper, and the influence onits electrical and thermal performance is experimentallyevaluated. Finally it is concluded thateven though the modified module show significantadvantages in turn-on switching energy, anincrease in turn-off energy offsets it while alsoachieving a worse thermal performance.
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