EPE Association: EPE 2022 - LS5a: Integration

EPE 2022 - LS5a: Integration
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2022 ECCE Europe - Conference > EPE 2022 - Topic 01: Devices, Packaging and System Integration > EPE 2022 - LS5a: Integration

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   Characterization of GaN-on-AlN/SiC transistors towards monolithic integrability
By Nick WIECZOREK [View]
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Abstract: A GaN-on-AlN/SiC technology is proposed for monolithic GaN power switch integration. As opposed to conventional GaN-on-Si devices, the insulating SiC substrate results in immunity to back-gating effects and enables monolithic integration without degradation of switching characteristics resulting from the shared substrate. This is validated for a discrete half-bridge, with the substrate of both transistors shorted together, as well as for a monolithic half-bridge. Hard switching transients up to 300 V in a double-pulse test with both half-bridges reveal faster switching transients and reduced switching losses for the monolithically integrated half-bridge.

   Design, implementation and characterization of an integrated current sensing in GaN HEMT device by using the current-mirroring technique
By Van Sang NGUYEN [View]
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Abstract: Based on wide bandgap devices (WBG) characterization constraints, this work presents the design, implementation and characterization of an integrated current sensor in a GaN HEMT (Gallium Nitride High-Electron-Mobility Transistor) by using the current-mirroring technique. Two HEMTs are implemented in this design; the compromised between the size ratio of these two transistors in the current-mirroring circuit and the sensitivity of the sensor are taken into account on the device design phase. In the implementation phase, the auxiliary components are optimized for the operation of the sensor, and then the circuit with the integrated current sensing in GaN power device is characterized with a high temperature double pulse test method, up to 175°C.

   Efficiently Paralleling GaN-Transistors for High Current and High Frequency Applications Using a Butterfly Layout
By Martin WATTENBERG [View]
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Abstract: This paper presents a scalable design for up to 8 GaN transistors per switch in a three-phase motor drive.To minimize the layout related issues, a fully symmetrical 'butterfly' layout was considered. Anexperimental three-phase prototype with a total of 8 chips per switch was built to verify the concept.Due to the highly symmetrical nature, this work focuses on four half-bridges in parallel, i.e. 4 chips perswitch. For evaluation, the design is operated as a 100 kHz buck converter with 50\% duty cycle. At 24and 48 V output currents up to 100 and 60 A respectively are achieved reliably. Measured voltagetransition times of 6 ns for all devices and minimal variations between device's temperature (_) of 12 and 5 K for 24 V/100 A and 48 V/ 60 A respectively confirm a correct operation.

EPE 2022 - LS5a: Integration
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2022 ECCE Europe - Conference > EPE 2022 - Topic 01: Devices, Packaging and System Integration > EPE 2022 - LS5a: Integration
	[return to parent folder]

	Characterization of GaN-on-AlN/SiC transistors towards monolithic integrability By Nick WIECZOREK	[View] [Download]
Abstract: A GaN-on-AlN/SiC technology is proposed for monolithic GaN power switch integration. As opposed to conventional GaN-on-Si devices, the insulating SiC substrate results in immunity to back-gating effects and enables monolithic integration without degradation of switching characteristics resulting from the shared substrate. This is validated for a discrete half-bridge, with the substrate of both transistors shorted together, as well as for a monolithic half-bridge. Hard switching transients up to 300 V in a double-pulse test with both half-bridges reveal faster switching transients and reduced switching losses for the monolithically integrated half-bridge.

	Design, implementation and characterization of an integrated current sensing in GaN HEMT device by using the current-mirroring technique By Van Sang NGUYEN	[View] [Download]
Abstract: Based on wide bandgap devices (WBG) characterization constraints, this work presents the design, implementation and characterization of an integrated current sensor in a GaN HEMT (Gallium Nitride High-Electron-Mobility Transistor) by using the current-mirroring technique. Two HEMTs are implemented in this design; the compromised between the size ratio of these two transistors in the current-mirroring circuit and the sensitivity of the sensor are taken into account on the device design phase. In the implementation phase, the auxiliary components are optimized for the operation of the sensor, and then the circuit with the integrated current sensing in GaN power device is characterized with a high temperature double pulse test method, up to 175°C.

	Efficiently Paralleling GaN-Transistors for High Current and High Frequency Applications Using a Butterfly Layout By Martin WATTENBERG	[View] [Download]
Abstract: This paper presents a scalable design for up to 8 GaN transistors per switch in a three-phase motor drive.To minimize the layout related issues, a fully symmetrical 'butterfly' layout was considered. Anexperimental three-phase prototype with a total of 8 chips per switch was built to verify the concept.Due to the highly symmetrical nature, this work focuses on four half-bridges in parallel, i.e. 4 chips perswitch. For evaluation, the design is operated as a 100 kHz buck converter with 50\% duty cycle. At 24and 48 V output currents up to 100 and 60 A respectively are achieved reliably. Measured voltagetransition times of 6 ns for all devices and minimal variations between device's temperature (_) of 12 and 5 K for 24 V/100 A and 48 V/ 60 A respectively confirm a correct operation.