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   Efficiently Paralleling GaN-Transistors for High Current and High Frequency Applications Using a Butterfly Layout   [View] 
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 Author(s)   Martin WATTENBERG 
 Abstract   This paper presents a scalable design for up to 8 GaN transistors per switch in a three-phase motor drive.To minimize the layout related issues, a fully symmetrical 'butterfly' layout was considered. Anexperimental three-phase prototype with a total of 8 chips per switch was built to verify the concept.Due to the highly symmetrical nature, this work focuses on four half-bridges in parallel, i.e. 4 chips perswitch. For evaluation, the design is operated as a 100 kHz buck converter with 50\% duty cycle. At 24and 48 V output currents up to 100 and 60 A respectively are achieved reliably. Measured voltagetransition times of 6 ns for all devices and minimal variations between device's temperature (_) of 12 and 5 K for 24 V/100 A and 48 V/ 60 A respectively confirm a correct operation. 
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Filename:0131-epe2022-full-13452788.pdf
Filesize:1.666 MB
 Type   Members Only 
 Date   Last modified 2023-09-24 by System