EPE Association: 08 - Madep - M2.1

08 - Madep - M2.1 - POWER IC's 02
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1991 - EPE-MADEP Joint Sessions > 08 - Madep - M2.1 - POWER IC's 02

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   DESIGN OF A BURIED DRAIN STRUCTURE FOR OPTIMUM PERFORMANCE OF SMART POWER IC's
By R. Zambrano; G. Percolla; F. Alberio [View]
[Download]

Abstract: In this paper a significant improvement to VIPower M2 structure is presented, which consists in the introduction of a "buried drain" region beneath the VDMOS power stage. This region is defined by means of a selective phosphorous implant, which, together with the n-type buried layer, provides a low resistance path for the drain current. The results of the electrical characterization are then commented, the measured data demonstrate the effectiveness of this region in achieving a dramatic reduction of the specific on resistance (Ron) Value, without affecting the breakdown voltage. The crystallographic quality has then been studied, the presence of the two low resistance buried layers doesn't translate into increased induced defect density, making it possible the integration of 60 Volts rated devices able to handle currents in the 50 to 100 Amperes range.

   VERTICAL PNP TRANSISTORS FOR POWER ICs IN HIGH SIDE DRIVER APPLICATIONS
By R. Zambrano [View]
[Download]

Abstract: In this paper the structure and the results of the electrical characterization of fully isolated vertical PNP transistors (VPNPs) are presented. These components can be used by devices made in VIPower (Vertical Intelligent Power) M2 technology, in all High Side Driver applications, thanks to an isolation structure based on the use of a p-type buried layer, fully enclosed in n-type, lightly doped epitaxial layers, needed as collector / drain of the vertical current flow power stage. The VPNP collector and base regions are the self-isolated p-type buried layer and the overlaying portion of the upper epilayer, respectively, while a p+ diffusion serves as emitter. A selective, low dose phosphorous implant can be considered to enhance the base doping concentration, such a structure ensures good DC performance and increases the VPNPs cut-off frequencies to values up to 50 times better than those of their lateral counterparts.

   AN INTRINSIC SAVE SMART POWER IGBT
By R. Gabriel [View]
[Download]

Abstract: SOI technology enables the integration of vertical power transistors and Smart Power features like gate drive, overcurrent and overtemperature shutdown circuitry. Using dielectric isolation technics virtually all power transistor families and integrated circuit technologies can be merged. Due to the good conformity to standard semiconductor technologies Iike DMOS and CMOS it seems to be a good candidate for future high voltage smart power technologies. The benefits and limitations of this technology will be discussed with a high voltage smart power IGBT using SOI technology. The power transistor is of the IGBT type enabling a higher current density compared to MOS devices.

   INVESTIGATIONS TO INTEGRATE A BRUSHLESS DC MOTOR DRIVE IC FOR LOW SUPPLY VOLTAGES
By Armin Wegener [View]
[Download]

Abstract: This paper reports about the investigations to integrate a driver IC to operate a sensorless, electronically commutated three phase DC motor with permanent magnets. The drive IC should work at very low supply voltage between 2V and 5V and should deliver a power of up to 4W to the motor. The specifications of such a drive IC are summarized and used for a comparative study of bipolar, standard CMOS and BiCMOS processes. One of the main objectives is the integration of 3 half-bridge circuits comprising 6 transistors each featuring an "on-resistance" Ron of 100 to 150mOhm. Therefore an evaluation chip containing one half-bridge circuit was fabricated in the BiCMOS process. The detailed analysis revealed the first order parameters contributing to the total Ron. which are the active device area, metallization, bond wires and leadframe.

   DRIVING AND PROTECTION CIRCUITRY FOR A SMART POWER MOS HIGH-SIDE SWITCH BASED ON A FLOATING WELL CONCEPT
By M. Bafleur; J. Buxo; Ph. Givelin; V. Macary [View]
[Download]

Abstract: This paper presents a new driving circuitry for MOS power high-side switch which is based on a single epitaxy CMOS/DMOS technology and a floating well concept. lt is shown that this latter concept allows to avoid latch-up initiation and use of parasitic vertical bipolar transistor as an active device. This parasitic device is advantageously used in the proposed driving circuit. lndeed, it permitS to achieve fast charging of the DMOS gate in a very compact form and to obtain power device protection during the discharge of an inductive load. These circuits have been studied with the aid of SPICE simulations using macromodels for the DMOS device.

   A PROGRAMMABLE LIGHTNlNG PROTECTOR FOR SUBSCRIBER LlNE INTERFACE CIRCUIT (SLIC)
By R. Pezzani; E. Bernier; A. Bremond [View]
[Download]

Abstract: This paper presents a programmable crowbar device dedicated to protect, in telecom area, SLIC from lightning risk, power line crosses and other parasitic voltages on the subscriber line. This device is realized with bipolar technology in monolithic configuration and gives key advantages for a maximum surge current capability, a very sensitive gate triggering and an high holding current. The approach of this surge suppressor can be extended to a double gates structure allowing a protection between a negative and positive adjustable voltage bipolar technology in monolithic configuration.

08 - Madep - M2.1 - POWER IC's 02
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1991 - EPE-MADEP Joint Sessions > 08 - Madep - M2.1 - POWER IC's 02
	[return to parent folder]

	DESIGN OF A BURIED DRAIN STRUCTURE FOR OPTIMUM PERFORMANCE OF SMART POWER IC's By R. Zambrano; G. Percolla; F. Alberio	[View] [Download]
Abstract: In this paper a significant improvement to VIPower M2 structure is presented, which consists in the introduction of a "buried drain" region beneath the VDMOS power stage. This region is defined by means of a selective phosphorous implant, which, together with the n-type buried layer, provides a low resistance path for the drain current. The results of the electrical characterization are then commented, the measured data demonstrate the effectiveness of this region in achieving a dramatic reduction of the specific on resistance (Ron) Value, without affecting the breakdown voltage. The crystallographic quality has then been studied, the presence of the two low resistance buried layers doesn't translate into increased induced defect density, making it possible the integration of 60 Volts rated devices able to handle currents in the 50 to 100 Amperes range.

	VERTICAL PNP TRANSISTORS FOR POWER ICs IN HIGH SIDE DRIVER APPLICATIONS By R. Zambrano	[View] [Download]
Abstract: In this paper the structure and the results of the electrical characterization of fully isolated vertical PNP transistors (VPNPs) are presented. These components can be used by devices made in VIPower (Vertical Intelligent Power) M2 technology, in all High Side Driver applications, thanks to an isolation structure based on the use of a p-type buried layer, fully enclosed in n-type, lightly doped epitaxial layers, needed as collector / drain of the vertical current flow power stage. The VPNP collector and base regions are the self-isolated p-type buried layer and the overlaying portion of the upper epilayer, respectively, while a p+ diffusion serves as emitter. A selective, low dose phosphorous implant can be considered to enhance the base doping concentration, such a structure ensures good DC performance and increases the VPNPs cut-off frequencies to values up to 50 times better than those of their lateral counterparts.

	AN INTRINSIC SAVE SMART POWER IGBT By R. Gabriel	[View] [Download]
Abstract: SOI technology enables the integration of vertical power transistors and Smart Power features like gate drive, overcurrent and overtemperature shutdown circuitry. Using dielectric isolation technics virtually all power transistor families and integrated circuit technologies can be merged. Due to the good conformity to standard semiconductor technologies Iike DMOS and CMOS it seems to be a good candidate for future high voltage smart power technologies. The benefits and limitations of this technology will be discussed with a high voltage smart power IGBT using SOI technology. The power transistor is of the IGBT type enabling a higher current density compared to MOS devices.

	INVESTIGATIONS TO INTEGRATE A BRUSHLESS DC MOTOR DRIVE IC FOR LOW SUPPLY VOLTAGES By Armin Wegener	[View] [Download]
Abstract: This paper reports about the investigations to integrate a driver IC to operate a sensorless, electronically commutated three phase DC motor with permanent magnets. The drive IC should work at very low supply voltage between 2V and 5V and should deliver a power of up to 4W to the motor. The specifications of such a drive IC are summarized and used for a comparative study of bipolar, standard CMOS and BiCMOS processes. One of the main objectives is the integration of 3 half-bridge circuits comprising 6 transistors each featuring an "on-resistance" Ron of 100 to 150mOhm. Therefore an evaluation chip containing one half-bridge circuit was fabricated in the BiCMOS process. The detailed analysis revealed the first order parameters contributing to the total Ron. which are the active device area, metallization, bond wires and leadframe.

	DRIVING AND PROTECTION CIRCUITRY FOR A SMART POWER MOS HIGH-SIDE SWITCH BASED ON A FLOATING WELL CONCEPT By M. Bafleur; J. Buxo; Ph. Givelin; V. Macary	[View] [Download]
Abstract: This paper presents a new driving circuitry for MOS power high-side switch which is based on a single epitaxy CMOS/DMOS technology and a floating well concept. lt is shown that this latter concept allows to avoid latch-up initiation and use of parasitic vertical bipolar transistor as an active device. This parasitic device is advantageously used in the proposed driving circuit. lndeed, it permitS to achieve fast charging of the DMOS gate in a very compact form and to obtain power device protection during the discharge of an inductive load. These circuits have been studied with the aid of SPICE simulations using macromodels for the DMOS device.

	A PROGRAMMABLE LIGHTNlNG PROTECTOR FOR SUBSCRIBER LlNE INTERFACE CIRCUIT (SLIC) By R. Pezzani; E. Bernier; A. Bremond	[View] [Download]
Abstract: This paper presents a programmable crowbar device dedicated to protect, in telecom area, SLIC from lightning risk, power line crosses and other parasitic voltages on the subscriber line. This device is realized with bipolar technology in monolithic configuration and gives key advantages for a maximum surge current capability, a very sensitive gate triggering and an high holding current. The approach of this surge suppressor can be extended to a double gates structure allowing a protection between a negative and positive adjustable voltage bipolar technology in monolithic configuration.