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   DESIGN OF A BURIED DRAIN STRUCTURE FOR OPTIMUM PERFORMANCE OF SMART POWER IC's   [View] 
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 Author(s)   R. Zambrano; G. Percolla; F. Alberio 
 Abstract   In this paper a significant improvement to VIPower M2 structure is presented, which consists in the introduction of a "buried drain" region beneath the VDMOS power stage. This region is defined by means of a selective phosphorous implant, which, together with the n-type buried layer, provides a low resistance path for the drain current. The results of the electrical characterization are then commented, the measured data demonstrate the effectiveness of this region in achieving a dramatic reduction of the specific on resistance (Ron) Value, without affecting the breakdown voltage. The crystallographic quality has then been studied, the presence of the two low resistance buried layers doesn't translate into increased induced defect density, making it possible the integration of 60 Volts rated devices able to handle currents in the 50 to 100 Amperes range. 
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Filename:Unnamed file
Filesize:2.17 MB
 Type   Members Only 
 Date   Last modified 2019-06-11 by System