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 04 - Madep - M04 - MATERIAL AND PROCESSES 04 
 You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1991 - EPE-MADEP Joint Sessions > 04 - Madep - M04 - MATERIAL AND PROCESSES 04 
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   DIAGRAMS FOR CALCULATING THE VIRTUAL JUNCTION TEMPERATURE RIPPLE OF SEMICONDUCTOR DEVICES 
 By Z. Bencic; D. Ilic-Roller 
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Abstract: Diagrams for constant pulse current with rectangular and sinusoidal wave forms were calculated. They are designed to calculate the difference between virtual junction temperature at the end and at the beginning of current pulse. The described method is valid for all semiconductor devices whose thermal circuit can be modeled electrically by serial RC-pair connection whose forward characteristic can be approximated by threshold voltage and slope resistance. The use of diagrams is illustrated.

 
   ELECTRON IRRADIATION OF POWER DIODES. COMPARISON BETWEEN FZ AND MCZ SILICON SUBSTRATES 
 By P. G. Fuochi; E. Gombia; R. Mosca; F. Fasce; M. lcardi; M. Portesine; P. Rossetto 
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Abstract: A study of the influence of the starting material (float-zone (FZ) and magnetic Czochralski (MCZ) n-type silicon) and of the device processing on the characteristics of high power p-i-n diodes has been made. Lifetime reduction was achieved by 12 Mev electron irradiation. The static and dynamic electrical characteristics as well as the deep level evaluation are reported. A comparison of the results obtained from FZ and MCZ p-i-n diodes indicates that no significant difference between the two substrates exists as far as the electrical characteristics of the devices as well as the nature and concentration of deep levels are concerned.

 
   PROCESS CONTROL AND IMPROVEMENT IN HIGH POWER SEMICONDUCTOR MANUFACTURE USING SCANNING ACOUSTIC MICROSCOPY 
 By J. Attal; A. Cambiaso; D. E. Crees; P. Dargent; F. Fasce; M. Grattarola; D. R. Newcombe; J. C. Noack; J. M. Saurel; M. Zambelli 
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Abstract: Object of this work was the use of Scanning Acoustic Microscopy (SAM) to identify and characterise defects in power semiconductor devices, particularly in p-i-n diodes, bipolar junction transistors (BJT), silicon controlled rectifiers (SCR), and gate turn-off thyristors (GTO). Defects like impurities in the crystal, microcracking in the silicon wafer, voids at the silicon/metallisation interface, are inevitably introduced at various stages of the manufacturing process, and these strongly affect the electrical performance of the device. Since high voltage and current ratings are required from very large area devices, an accurate knowledge of the defects introduced during processing is a key factor for obtaining reasonable yields in manufacturing. SAM was seen as a candidate non-destructive technique for the identification at an early stage in the fabrication process of defects that may affect the electrical performance of the device. This paper reports the results obtained during a two years research project, carried out under the auspices of the European Community's BRITE Programme, whose aim was the development of non-destructive test methods for on-line process monitoring of high power semiconductor device manufacture.

 
   GROWTH OF LARGE DIAMETER HIGH PURITY SILICON SINGLE CRYSTALS WITH THE MCZ METHOD FOR POWER DEVICES APPLICATIONS 
 By Maria Porrini; Pietro Rossetto 
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Abstract: This paper reports the recent results of our researches on MCZ crystal growth, which have shown the feasibility of growing crystals up to 150 mm in diameter under a transverse magnetic field with consistent bulk properties such as a low oxygen content, less than 7 ppma new ASTM along all its length, and a low resistivity radial gradient. It is also shown that the MCZ technique has superior capabilities for producing high resistivity and high purity crystals than the conventional CZ technique. It is shown, both through theoretical calculations and experimental results, that the application of a transverse magnetic field to a CZ pulling apparatus reduces the crucible dissolution rate, thus reducing the impurities incorporation rate into the growing crystal.

 
   SILICON-ON-INSULATOR THICK FILMS PREPARED BY ZONE MELTING RECRYSTALLIZATION FOR HIGH VOLTAGE DEVICES 
 By R. Banisch; B. Tillack; H. H. Richter; K. Höppner; O. Joachim 
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Abstract: SOI wafers with full dielectrically isolated island are prepared by zone melting recrystallization of a polycrystalline film deposited on a non planar silicon substrate covered with Si02 and following planarization of the wafer surface. High voltage MOS and bipolar transistors are prepared on the substrates. The transistor parameters, taken as a measure of the crystal quality, were in the technologically expected range. The breakdown voltage of the isolation oxid was about 400 V. The electrical characterization as well as crystallographic investigations demonstrate the good quality of the ZMR SOI wafers and their potential use for high voltage applications.