EPE Association: EPE 2017 - DS1b: New materials and Active Devices

EPE 2017 - DS1b: New materials and Active Devices
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2017 ECCE Europe - Conference > EPE 2017 - Topic 01: Devices, Packaging and System Integration > EPE 2017 - DS1b: New materials and Active Devices

   [return to parent folder]

   Common mode current mitigation for Medium Voltage Half Bridge SiC Modules
By Nicklas CHRISTENSEN [View]
[Download]

Abstract: Medium voltage 10 kV Silicon Carbide MOSFETs, introduce challenges regarding converter design. Very high rate of voltage change and capacitive couplings to for example cooling systems cause increased electromagnetic interference. The aim of this paper is to accurately model the capacitive coupling to a heat sink and experimentally validate the model. An analytic model of the heat sink is developed which is demonstrated to be in excellent agreement with experimental results. The experimental result validates the modelled heat sink network allowing engineers to choose a suitable grounding impedance to comply with the electromagnetic compatibility regulations.

   Experimental Study on Fast-Switching Series-Connected SiC MOSFETs
By RAFAL KOPACZ [View]
[Download]

Abstract: This paper presents an experimental study on series-connection of Silicon Carbide MOSFETs. The switching performance of two series-connected SiC MOSFETs rated at 1200 V and having on-state resistances of 80 m_ was tested using a double-pulse test circuit at blocking voltages up to 1 kV DC and currents up to 50 A. The design and experimental validation of a suitable double-pulse test setup and gate drive circuits are also shown. Moreover, the impact of additional DRC snubbers ensuring an equal voltage sharing among the series-connected transistors is also investigated.

   Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter
By Dipen DALAL [View]
[Download]

Abstract: This paper investigates gate driver design challenges encountered due to the fast switching transients in medium voltage half bridge silicon carbide MOSFET power modules. The paper presents, design of a reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification and detailed test results are presented to validate the gate driver functionality. The designed gate driver circuit shows satisfactory performance with increased common mode noise immunity and protection against the Miller current induced unwanted turn on.

   Hard and Soft Switching Losses of a SiC MOSFET Module under Realistic Topology and Loading Conditions
By Subhadra TIWARI [View]
[Download]

Abstract: This paper investigates the switching performance of a 1.2 kV half-bridge SiC MOSFET module fromSanrex. Unlike in a standard SiC MOSFET module, where the MOSFET and the anti-parallel diode chipsare fabricated separately, in the chosen MOSFET module (FCA150XB120), both the MOSFET and thediode are fabricated on a single chip. The device is characterized under both hard and soft switchingconditions. For the hard switching characterization, an inductive clamped buck converter is employed,whereas for the soft switching characterization, a resonant half-bridge converter with LC load is used.A comparison of the hard switching loss is performed with the soft switching loss at the same current.This comparison provides insight into the significance of employing an appropriate circuit topology,load and control scheme to reflect the waveforms as in a real application, in order to get a more accurateassessment of the switching losses that will occur. This insight is the main contribution of this paper.

   Parasitic capacitances and inductances hindering utilization of the fast switching potential of SiC power modules. Simulation model verified by experiment.
By Subhadra TIWARI [View]
[Download]

Abstract: This paper investigates the switching performances of two state-of-the-art half-bridge SiC MOSFETmodules using a standard double pulse test methodology. A deliberate choice of the modules with thesame voltage and current ratings, the same packaging, but different stray inductances and capacitancesis made in order to give an insight into the influence of parasitics in the switching transients and energylosses. A circuit simulation is performed with varying stray parameters in an LTSpice to illustrate theimpact of parasitics in both voltage and current waveforms. Thereafter, a detailed comparison betweenthe two modules is presented at similar dv/dt and di/dt conditions through laboratory measurements. Theexperimental results confirm the simulation results, giving a clear message that parasitic capacitances andinductances hinder the fast switching potential of SiC power modules. Furthermore, the performance ofdevice with different voltage ratings can be anticipated using this parametric study. Thus, the analysisand understanding of parasitics, and their influence on switching performance is vital in the choice ofan appropriate SiC MOSFET module for a particular application. The present paper contributes in thisregard.

   Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM
By Asger Bjørn JØRGENSEN [View]
[Download]

Abstract: The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.

EPE 2017 - DS1b: New materials and Active Devices
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2017 ECCE Europe - Conference > EPE 2017 - Topic 01: Devices, Packaging and System Integration > EPE 2017 - DS1b: New materials and Active Devices
	[return to parent folder]

	Common mode current mitigation for Medium Voltage Half Bridge SiC Modules By Nicklas CHRISTENSEN	[View] [Download]
Abstract: Medium voltage 10 kV Silicon Carbide MOSFETs, introduce challenges regarding converter design. Very high rate of voltage change and capacitive couplings to for example cooling systems cause increased electromagnetic interference. The aim of this paper is to accurately model the capacitive coupling to a heat sink and experimentally validate the model. An analytic model of the heat sink is developed which is demonstrated to be in excellent agreement with experimental results. The experimental result validates the modelled heat sink network allowing engineers to choose a suitable grounding impedance to comply with the electromagnetic compatibility regulations.

	Experimental Study on Fast-Switching Series-Connected SiC MOSFETs By RAFAL KOPACZ	[View] [Download]
Abstract: This paper presents an experimental study on series-connection of Silicon Carbide MOSFETs. The switching performance of two series-connected SiC MOSFETs rated at 1200 V and having on-state resistances of 80 m_ was tested using a double-pulse test circuit at blocking voltages up to 1 kV DC and currents up to 50 A. The design and experimental validation of a suitable double-pulse test setup and gate drive circuits are also shown. Moreover, the impact of additional DRC snubbers ensuring an equal voltage sharing among the series-connected transistors is also investigated.

	Gate driver with high common mode rejection and self turn-on mitigation for a 10 kV SiC MOSFET enabled MV converter By Dipen DALAL	[View] [Download]
Abstract: This paper investigates gate driver design challenges encountered due to the fast switching transients in medium voltage half bridge silicon carbide MOSFET power modules. The paper presents, design of a reduced isolation capacitance regulated DC-DC power supply and a gate driver with an active Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification and detailed test results are presented to validate the gate driver functionality. The designed gate driver circuit shows satisfactory performance with increased common mode noise immunity and protection against the Miller current induced unwanted turn on.

	Hard and Soft Switching Losses of a SiC MOSFET Module under Realistic Topology and Loading Conditions By Subhadra TIWARI	[View] [Download]
Abstract: This paper investigates the switching performance of a 1.2 kV half-bridge SiC MOSFET module fromSanrex. Unlike in a standard SiC MOSFET module, where the MOSFET and the anti-parallel diode chipsare fabricated separately, in the chosen MOSFET module (FCA150XB120), both the MOSFET and thediode are fabricated on a single chip. The device is characterized under both hard and soft switchingconditions. For the hard switching characterization, an inductive clamped buck converter is employed,whereas for the soft switching characterization, a resonant half-bridge converter with LC load is used.A comparison of the hard switching loss is performed with the soft switching loss at the same current.This comparison provides insight into the significance of employing an appropriate circuit topology,load and control scheme to reflect the waveforms as in a real application, in order to get a more accurateassessment of the switching losses that will occur. This insight is the main contribution of this paper.

	Parasitic capacitances and inductances hindering utilization of the fast switching potential of SiC power modules. Simulation model verified by experiment. By Subhadra TIWARI	[View] [Download]
Abstract: This paper investigates the switching performances of two state-of-the-art half-bridge SiC MOSFETmodules using a standard double pulse test methodology. A deliberate choice of the modules with thesame voltage and current ratings, the same packaging, but different stray inductances and capacitancesis made in order to give an insight into the influence of parasitics in the switching transients and energylosses. A circuit simulation is performed with varying stray parameters in an LTSpice to illustrate theimpact of parasitics in both voltage and current waveforms. Thereafter, a detailed comparison betweenthe two modules is presented at similar dv/dt and di/dt conditions through laboratory measurements. Theexperimental results confirm the simulation results, giving a clear message that parasitic capacitances andinductances hinder the fast switching potential of SiC power modules. Furthermore, the performance ofdevice with different voltage ratings can be anticipated using this parametric study. Thus, the analysisand understanding of parasitics, and their influence on switching performance is vital in the choice ofan appropriate SiC MOSFET module for a particular application. The present paper contributes in thisregard.

	Reduction of parasitic capacitance in 10 kV SiC MOSFET power modules using 3D FEM By Asger Bjørn JØRGENSEN	[View] [Download]
Abstract: The benefits of emerging wide-band gap semiconductors can only be utilized if the semiconductor is properly packaged. Capacitive coupling in the package causes electromagnetic interference during high dv/dt switching. This paper investigates the current flowing in the parasitic capacitance between the output node and the grounded heat sink for a custom silicon carbide power module. A circuit model of the capacitive coupling path is presented, using parasitic capacitances extracted from ANSYS Q3D. Simulated values are compared with experimental results. A new iteration of the silicon carbide power module is designed, having reduced capacitive coupling without penalizing other parameters. The new module is tested experimentally, which verifies the reduced capacitive coupling to the heat sink.