EPE Association: EPE 2014 - DS2b: New Materials and Active Devices

EPE 2014 - DS2b: New Materials and Active Devices
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2014 ECCE Europe - Conference > EPE 2014 - Topic 01: Devices, Packaging and System Integration > EPE 2014 - DS2b: New Materials and Active Devices

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   A Simple SiC JFET based AC variable current Limiter
By Werner KONRAD, Kennith LEONG, Klaus KRISCHAN, Annette MUETZE [View]
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Abstract: This paper proposes a simple AC solid state variable current limiter based on two commercially available 1200 V SiC JFETs [1], the JFET conguration requires no active regulation and has intrinsically fast response time to short circuit conditions with the benet of simplicity and low cost. This circuit is intended as an additional current limiting circuit for high power ampliers where the current limitation reaction time is in the seconds range. This demoboard was built for fast current limitation with high power ampliers to test PFC (Power Factor Correction) circuit. This paper presents the circuit of a working demonstrator with experimental verication and compares the experimental results with simulations.

   Experimental Analysis of Bipolar SiC-Devices for Future Electrical Energy Distribution Systems
By Andreas HUERNER, Heinz MITLEHNER, Tobias ERLBACHER, Anton BAUER, Lothar FREY [View]
[Download]

Abstract: In this study, the electrical performance of a bipolar switch (BiFET) fabricated on 4H-SiC proposed as solid state circuit breaker is discussed. Therefore, first results on the output and blocking characteristic are presented and analyzed. The bipolar switch indicates a current limiting output characteristic and robust behavior in off-state mode. Nevertheless, further improvement of the conduction properties by increasing the doping concentration in the p-type channel region has to be carried out. Furthermore, it is determined that for a clear understanding of the temperature dependency of the output characteristic, further investigations concerning the influence of the incomplete ionization, ambipolar lifetime, and emitter efficiency are mandatory.

   On the Application of Novel High Temperature Oxidation Processes to Enhance the Performance of High Voltage Silicon Carbide PiN Diodes
By Craig FISHER, Michael JENNINGS, Dean HAMILTON, Stephen THOMAS, Yogesh SHARMA, Peter GAMMON, Susan BURROWS, Philip MAWBY [View]
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Abstract: In this paper, the application of a combined high temperature (1550_C) thermal oxidation / annealing process has been applied to 4H-SiC PiN diodes with 110 #956;m thick n-type drift regions, for the pur- pose of increasing the carrier lifetime in the semiconductor. PiN diodes were fabricated on lifetime- enhanced 4H-SiC material, then were electrically characterised and compared against fabricated control sample PiN diodes. Forward current-voltage (I-V) measurements showed that the lifetime-enhanced de- vices typically had around 15\% lower forward voltage drop and 40\% lower differential on-resistance (at 100 A/cm2 and 25_C) when compared against control sample PiN diodes. Reverse I-V measurements indicated that the reverse leakage current was strongly dependent on the active area, and hence perimeter- to-area ratio, of the fabricated devices, though large-area PiN diodes were measured to have a reverse leakage current density of around 1 nA/cm2 (at 100 V reverse bias). Analysis of reverse recovery characteristics illustrated the excellent transient characteristics of both types of fabricated device, though, as expected from the increased carrier lifetime, the lifetime-enhanced PiN diodes had around 22\% higher reverse recovery charge. The minority carrier lifetime was also extracted from reverse recovery characteristics; PiN diodes fabricated on the lifetime-enhanced 4H-SiC material were found to have a carrier lifetime over 35\% higher than the control sample devices. Analysis of the overall power losses of both types of device found that the lifetime-enhanced PiN diodes typically dissipated around 40\% less energy over the complete switching cycle than the control sample PiN diodes at 25_C.

   Study of a novel lateral RESURF 3C-SiC on Si Schottky diode
By Fan LI, Yogesh SHARMA, Michael JENNINGS, Philip MAWBY, Craig FISHER, Hua RONG [View]
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Abstract: 3C-SiC can be grown on large area silicon substrates, thus potentially it can lower the cost of wide band gap power devices. However, the uncertain carrier transportation at the 3C-SiC/Si interface does not favour vertical device structures. A lateral design can avoid this problem without removing the substrate after epitaxial growth. In this work, a novel lateral charge compensation Schottky diode is modelled and studied using the finite element device simulator Silvaco. Compared with conventional lateral diodes, the simulation results for the proposed design demonstrate excellent performance with low specific on-resistance (#8776;4 mOhm.cm2) and high breakdown voltage (> 1200 V). The influences of 3C-SiC epilayer bulk traps, 3C-SiC/Si interface defects as well as the semiconductor surface charge on device performance are studied for practical fabrication considerations.

EPE 2014 - DS2b: New Materials and Active Devices
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2014 ECCE Europe - Conference > EPE 2014 - Topic 01: Devices, Packaging and System Integration > EPE 2014 - DS2b: New Materials and Active Devices
	[return to parent folder]

	A Simple SiC JFET based AC variable current Limiter By Werner KONRAD, Kennith LEONG, Klaus KRISCHAN, Annette MUETZE	[View] [Download]
Abstract: This paper proposes a simple AC solid state variable current limiter based on two commercially available 1200 V SiC JFETs [1], the JFET conguration requires no active regulation and has intrinsically fast response time to short circuit conditions with the benet of simplicity and low cost. This circuit is intended as an additional current limiting circuit for high power ampliers where the current limitation reaction time is in the seconds range. This demoboard was built for fast current limitation with high power ampliers to test PFC (Power Factor Correction) circuit. This paper presents the circuit of a working demonstrator with experimental verication and compares the experimental results with simulations.

	Experimental Analysis of Bipolar SiC-Devices for Future Electrical Energy Distribution Systems By Andreas HUERNER, Heinz MITLEHNER, Tobias ERLBACHER, Anton BAUER, Lothar FREY	[View] [Download]
Abstract: In this study, the electrical performance of a bipolar switch (BiFET) fabricated on 4H-SiC proposed as solid state circuit breaker is discussed. Therefore, first results on the output and blocking characteristic are presented and analyzed. The bipolar switch indicates a current limiting output characteristic and robust behavior in off-state mode. Nevertheless, further improvement of the conduction properties by increasing the doping concentration in the p-type channel region has to be carried out. Furthermore, it is determined that for a clear understanding of the temperature dependency of the output characteristic, further investigations concerning the influence of the incomplete ionization, ambipolar lifetime, and emitter efficiency are mandatory.

	On the Application of Novel High Temperature Oxidation Processes to Enhance the Performance of High Voltage Silicon Carbide PiN Diodes By Craig FISHER, Michael JENNINGS, Dean HAMILTON, Stephen THOMAS, Yogesh SHARMA, Peter GAMMON, Susan BURROWS, Philip MAWBY	[View] [Download]
Abstract: In this paper, the application of a combined high temperature (1550_C) thermal oxidation / annealing process has been applied to 4H-SiC PiN diodes with 110 #956;m thick n-type drift regions, for the pur- pose of increasing the carrier lifetime in the semiconductor. PiN diodes were fabricated on lifetime- enhanced 4H-SiC material, then were electrically characterised and compared against fabricated control sample PiN diodes. Forward current-voltage (I-V) measurements showed that the lifetime-enhanced de- vices typically had around 15\% lower forward voltage drop and 40\% lower differential on-resistance (at 100 A/cm2 and 25_C) when compared against control sample PiN diodes. Reverse I-V measurements indicated that the reverse leakage current was strongly dependent on the active area, and hence perimeter- to-area ratio, of the fabricated devices, though large-area PiN diodes were measured to have a reverse leakage current density of around 1 nA/cm2 (at 100 V reverse bias). Analysis of reverse recovery characteristics illustrated the excellent transient characteristics of both types of fabricated device, though, as expected from the increased carrier lifetime, the lifetime-enhanced PiN diodes had around 22\% higher reverse recovery charge. The minority carrier lifetime was also extracted from reverse recovery characteristics; PiN diodes fabricated on the lifetime-enhanced 4H-SiC material were found to have a carrier lifetime over 35\% higher than the control sample devices. Analysis of the overall power losses of both types of device found that the lifetime-enhanced PiN diodes typically dissipated around 40\% less energy over the complete switching cycle than the control sample PiN diodes at 25_C.

	Study of a novel lateral RESURF 3C-SiC on Si Schottky diode By Fan LI, Yogesh SHARMA, Michael JENNINGS, Philip MAWBY, Craig FISHER, Hua RONG	[View] [Download]
Abstract: 3C-SiC can be grown on large area silicon substrates, thus potentially it can lower the cost of wide band gap power devices. However, the uncertain carrier transportation at the 3C-SiC/Si interface does not favour vertical device structures. A lateral design can avoid this problem without removing the substrate after epitaxial growth. In this work, a novel lateral charge compensation Schottky diode is modelled and studied using the finite element device simulator Silvaco. Compared with conventional lateral diodes, the simulation results for the proposed design demonstrate excellent performance with low specific on-resistance (#8776;4 mOhm.cm2) and high breakdown voltage (> 1200 V). The influences of 3C-SiC epilayer bulk traps, 3C-SiC/Si interface defects as well as the semiconductor surface charge on device performance are studied for practical fabrication considerations.