EPE Association: EPE 1993 - 01 - Lecture Session L1a: INTEGRATED DEVICES

EPE 1993 - 01 - Lecture Session L1a: INTEGRATED DEVICES
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1993 - Conference > EPE 1993 - 01 - Lecture Session L1a: INTEGRATED DEVICES

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   IMPROVED STRUCTURES FOR POWER MOSFETs WITH ON-CHIP FULL PROTECTION
By R. Zambrano [View]
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Abstract: Power MOSFETs with built-in shorted load protection have been recently presented where a laterel npn transistor pulls down the gate to limit the drain current, but a parasitic verticel npn can limit the operating voltage below the power MOSFET's BVdss. Further structural modifications so far devised result in large power losses or strongly non-linear characteristics. Such drawbacks have been overcome by a new LNPN structure, or by an NMOSFET, whose performance are optimized with a dedicated implant. The devices with bipolar-based feedback network exhibit better limiting behaviour, but similar performance can be achieved by increasing the sense ratio in the NMOSFET-based devices. All the devices feature ESD protection and an active gate-drain damp to enhance ruggedness. The clamping voltage is set below the power MOSFET's BVdss, is independent of the epilayer parameters, and has a low temperature coefficient, thus resulting in very predictable performance.

   FUNCTIONAL INTEGRATION OF M.0.S AND THYRISTOR DEVICES: A USEFUL CONCEPT TO CREATE NEW LIGHT TRIGGERED INTEGRATED SWITCHES FOR POWER CONVERSION
By J-L. Sanchez; R. Berriane; J. Jalade; J.P. Laur [View]
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Abstract: In power electronics converters, a galvanic insulation between drive circuits and power stage is usually needed and it may be relatively delicate to implement it accordlng to the application considered . When high galvanic insulation is required, a good solution consists of integrating optical control detection circuits with each power device. lntegration is a natural way of enhancing design, performance and reliability, resulting in easier use. To illustrate this approach, we present in this paper a light triggered thyristor with a MOS amplifying gate whose conception is based on functional integration of MOS and thyristor elements. An application of this integrated switch in a power converter is also given.

   SUPERIOR SWITCHING BEHAVIOUR OF BIMOS TRANSISTOR IN DARLINGTON / PARALLEL COMBINATION
By D.K. Thakur; A. Kumar; P.D. Vyas; W.S. Khokle [View]
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Abstract: Lateral DMOS merged bipolar transistor, LDBIMOST, in Darlington / paralleled combinations has been fabricated using high resistivity p-substrate to handle large currents with superior speed. LDBIMOST has same structure as a lateral double-diffused MOS transistor (LDMOST) with p-body as a base of an active npn bipolar transistor. Device has been modelled using process and device computer program and circuit simulator to optimize the design to obtain a high breakdown voltage, low Ron and parasitic-free monolithic merged LDMOS bipolar structure. The influence of gate potential and gate metal over drift-region on Ron has been carried out. Several test structures of LDMOS with varying channel width have been designed to study electrical performance. It has been revealed that an additional integration of LDMOST along LDBIMOS transistor on same chip with minimum area concept has improved the turn-off speed of the device from 490 ns to 270 ns at current level of 1.3 Amp.

EPE 1993 - 01 - Lecture Session L1a: INTEGRATED DEVICES
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 1993 - Conference > EPE 1993 - 01 - Lecture Session L1a: INTEGRATED DEVICES
	[return to parent folder]

	IMPROVED STRUCTURES FOR POWER MOSFETs WITH ON-CHIP FULL PROTECTION By R. Zambrano	[View] [Download]
Abstract: Power MOSFETs with built-in shorted load protection have been recently presented where a laterel npn transistor pulls down the gate to limit the drain current, but a parasitic verticel npn can limit the operating voltage below the power MOSFET's BVdss. Further structural modifications so far devised result in large power losses or strongly non-linear characteristics. Such drawbacks have been overcome by a new LNPN structure, or by an NMOSFET, whose performance are optimized with a dedicated implant. The devices with bipolar-based feedback network exhibit better limiting behaviour, but similar performance can be achieved by increasing the sense ratio in the NMOSFET-based devices. All the devices feature ESD protection and an active gate-drain damp to enhance ruggedness. The clamping voltage is set below the power MOSFET's BVdss, is independent of the epilayer parameters, and has a low temperature coefficient, thus resulting in very predictable performance.

	FUNCTIONAL INTEGRATION OF M.0.S AND THYRISTOR DEVICES: A USEFUL CONCEPT TO CREATE NEW LIGHT TRIGGERED INTEGRATED SWITCHES FOR POWER CONVERSION By J-L. Sanchez; R. Berriane; J. Jalade; J.P. Laur	[View] [Download]
Abstract: In power electronics converters, a galvanic insulation between drive circuits and power stage is usually needed and it may be relatively delicate to implement it accordlng to the application considered . When high galvanic insulation is required, a good solution consists of integrating optical control detection circuits with each power device. lntegration is a natural way of enhancing design, performance and reliability, resulting in easier use. To illustrate this approach, we present in this paper a light triggered thyristor with a MOS amplifying gate whose conception is based on functional integration of MOS and thyristor elements. An application of this integrated switch in a power converter is also given.

	SUPERIOR SWITCHING BEHAVIOUR OF BIMOS TRANSISTOR IN DARLINGTON / PARALLEL COMBINATION By D.K. Thakur; A. Kumar; P.D. Vyas; W.S. Khokle	[View] [Download]
Abstract: Lateral DMOS merged bipolar transistor, LDBIMOST, in Darlington / paralleled combinations has been fabricated using high resistivity p-substrate to handle large currents with superior speed. LDBIMOST has same structure as a lateral double-diffused MOS transistor (LDMOST) with p-body as a base of an active npn bipolar transistor. Device has been modelled using process and device computer program and circuit simulator to optimize the design to obtain a high breakdown voltage, low Ron and parasitic-free monolithic merged LDMOS bipolar structure. The influence of gate potential and gate metal over drift-region on Ron has been carried out. Several test structures of LDMOS with varying channel width have been designed to study electrical performance. It has been revealed that an additional integration of LDMOST along LDBIMOS transistor on same chip with minimum area concept has improved the turn-off speed of the device from 490 ns to 270 ns at current level of 1.3 Amp.