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   IMPROVED STRUCTURES FOR POWER MOSFETs WITH ON-CHIP FULL PROTECTION   [View] 
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 Author(s)   R. Zambrano 
 Abstract   Power MOSFETs with built-in shorted load protection have been recently presented where a laterel npn transistor pulls down the gate to limit the drain current, but a parasitic verticel npn can limit the operating voltage below the power MOSFET's BVdss. Further structural modifications so far devised result in large power losses or strongly non-linear characteristics. Such drawbacks have been overcome by a new LNPN structure, or by an NMOSFET, whose performance are optimized with a dedicated implant. The devices with bipolar-based feedback network exhibit better limiting behaviour, but similar performance can be achieved by increasing the sense ratio in the NMOSFET-based devices. All the devices feature ESD protection and an active gate-drain damp to enhance ruggedness. The clamping voltage is set below the power MOSFET's BVdss, is independent of the epilayer parameters, and has a low temperature coefficient, thus resulting in very predictable performance. 
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Filename:Unnamed file
Filesize:1.912 MB
 Type   Members Only 
 Date   Last modified 2019-05-02 by System