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SUPERIOR SWITCHING BEHAVIOUR OF BIMOS TRANSISTOR IN DARLINGTON / PARALLEL COMBINATION
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| Author(s) |
D.K. Thakur; A. Kumar; P.D. Vyas; W.S. Khokle |
| Abstract |
Lateral DMOS merged bipolar transistor, LDBIMOST, in Darlington / paralleled combinations has been fabricated using high resistivity p-substrate to handle large currents with superior speed. LDBIMOST has same structure as a lateral double-diffused MOS transistor (LDMOST) with p-body as a base of an active npn bipolar transistor. Device has been modelled using process and device computer program and circuit simulator to optimize the design to obtain a high breakdown voltage, low Ron and parasitic-free monolithic merged LDMOS bipolar structure. The influence of gate potential and gate metal over drift-region on Ron has been carried out. Several test structures of LDMOS with varying channel width have been designed to study electrical performance. It has been revealed that an additional integration of LDMOST along LDBIMOS transistor on same chip with minimum area concept has improved the turn-off speed of the device from 490 ns to 270 ns at current level of 1.3 Amp. |
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| Filename: | Unnamed file |
| Filesize: | 2.662 MB |
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| Type |
Members Only |
| Date |
Last modified 2019-05-02 by System |
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