EPE Association: EPE 2017 - LS4e: SiC Devices

EPE 2017 - LS4e: SiC Devices
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2017 ECCE Europe - Conference > EPE 2017 - Topic 01: Devices, Packaging and System Integration > EPE 2017 - LS4e: SiC Devices

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   A SiC Trench MOSFET concept offering improved channel mobility and high reliability
By Ralf SIEMIENIEC [View]
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Abstract: This work discusses the challenges in the design of a SiC Power MOSFET compared to their silicon-based relatives and describes a novel SiC Trench MOSFET concept. The most prominent difficulties being identified are related to the properties of the channel and the gate dielectric as well as their interface. Different approaches to realize a SiC MOSFET are briefly discussed and the CoolSiC MOSFET concept is introduced which balances low conduction losses with an IGBT-like reliability. Long term gate oxide tests reveal that the extrinsic failure rate can be confidently predicted to be less than 1 FIT per die in 20 years under specified use conditions for industrial applications.

   Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn-on in low inductance power modules
By Andreas MAERZ [View]
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Abstract: In this paper different gate drive concepts to eliminate parasitic turn-on for SiC MOSFETs are discussed. Experimental results show a potential for lowering switching losses of SiC MOSFETs during fast switching operation, reduction of turn-off overvoltage across the bodydiode. Finally increased requirement on the gate drive unit are discussed.

   Design and Development of a High-Density, High-Speed 10 kV SiC MOSFET Module
By Christina DIMARINO [View]
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Abstract: High-density packaging of fast-switching power semiconductors typically requires low parasitic inductance, high heat extraction, and high thermo-mechanical reliability. High-density packaging of high-voltage power semiconductors, such as 10 kV SiC MOSFETs, also requires low electric field concentration in order to prevent premature dielectric breakdown. Consequently, in addition to the usual electromagnetic, thermal, and mechanical analyses, the electric fields must also be evaluated. This is the first detailed report on the optimization of a high-voltage SiC MOSFET power module.

   Failure Modes of Planar and Trench SiC MOSFETs under Single and Multiple Short Circuits Conditions
By Douglas PAPPIS [View]
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Abstract: An analysis of the failure modes due to short circuit on planar and trench $1200 V - 40 m\Omega$ SiC-MOSFETs is presented, including single and multiple events. Short circuit waveforms, energy, as well as electro-thermal simulations are presented, enabling the identification of the main root causes of failure. Results demonstrate similar performance regarding failure after turn-off (thermal runaway, gate) for both technologies, nevertheless the SiC-MOSFET trench variant showed superior response after multiple faults.

EPE 2017 - LS4e: SiC Devices
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2017 ECCE Europe - Conference > EPE 2017 - Topic 01: Devices, Packaging and System Integration > EPE 2017 - LS4e: SiC Devices
	[return to parent folder]

	A SiC Trench MOSFET concept offering improved channel mobility and high reliability By Ralf SIEMIENIEC	[View] [Download]
Abstract: This work discusses the challenges in the design of a SiC Power MOSFET compared to their silicon-based relatives and describes a novel SiC Trench MOSFET concept. The most prominent difficulties being identified are related to the properties of the channel and the gate dielectric as well as their interface. Different approaches to realize a SiC MOSFET are briefly discussed and the CoolSiC MOSFET concept is introduced which balances low conduction losses with an IGBT-like reliability. Long term gate oxide tests reveal that the extrinsic failure rate can be confidently predicted to be less than 1 FIT per die in 20 years under specified use conditions for industrial applications.

	Comparison of SiC MOSFET gate-drive concepts to suppress parasitic turn-on in low inductance power modules By Andreas MAERZ	[View] [Download]
Abstract: In this paper different gate drive concepts to eliminate parasitic turn-on for SiC MOSFETs are discussed. Experimental results show a potential for lowering switching losses of SiC MOSFETs during fast switching operation, reduction of turn-off overvoltage across the bodydiode. Finally increased requirement on the gate drive unit are discussed.

	Design and Development of a High-Density, High-Speed 10 kV SiC MOSFET Module By Christina DIMARINO	[View] [Download]
Abstract: High-density packaging of fast-switching power semiconductors typically requires low parasitic inductance, high heat extraction, and high thermo-mechanical reliability. High-density packaging of high-voltage power semiconductors, such as 10 kV SiC MOSFETs, also requires low electric field concentration in order to prevent premature dielectric breakdown. Consequently, in addition to the usual electromagnetic, thermal, and mechanical analyses, the electric fields must also be evaluated. This is the first detailed report on the optimization of a high-voltage SiC MOSFET power module.

	Failure Modes of Planar and Trench SiC MOSFETs under Single and Multiple Short Circuits Conditions By Douglas PAPPIS	[View] [Download]
Abstract: An analysis of the failure modes due to short circuit on planar and trench $1200 V - 40 m\Omega$ SiC-MOSFETs is presented, including single and multiple events. Short circuit waveforms, energy, as well as electro-thermal simulations are presented, enabling the identification of the main root causes of failure. Results demonstrate similar performance regarding failure after turn-off (thermal runaway, gate) for both technologies, nevertheless the SiC-MOSFET trench variant showed superior response after multiple faults.