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 EPE-PEMC 2000 - Topic 03b: Power Factor Correction 
 You are here: EPE Documents > 04 - EPE-PEMC Conference Proceedings > EPE-PEMC 2000 - Conference > EPE-PEMC 2000 - Topic 03: Control of Converters > EPE-PEMC 2000 - Topic 03b: Power Factor Correction 
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   A New Family of Power-Factor-Correction Sliding Mode Controllers Based on the Quasi-Steady-State Approach 
 By López O., García de Vicuna L., Matas J., Castilla M., López M. 
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Abstract: This paper proposes a new family of power-factor-correction sliding mode controllers. The proposed controllers are based on the quasi-steady-state approach of continuous-conduction-mode operating converters. Therefore, they are suitable for high-power-factor applications and constitute an interesting alternative to multiplier approach control scheme due to their simple implementation.

 
   DSP Control a ZVT Soft-Switching PFC Converter 
 By Ya-Tsung Feng, Yo-Ming Chen, Hsing-Fu Liu, Ying-Yu Tzou 
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Abstract: This paper presents the design of a DSP-controlled zero-voltage-transition power factor correction (PFC) converter used for high-performance communication equipment. The designed PFC converter can achieve high power factor with fast dynamic response for output voltage regulation. Zero-voltage-transition soft-switching technique has been applied to reduce the switching losses of the auxiliary switching circuit for a single-phase ac-dc converter with unit power factor. The operation principle, digital control scheme, and experimental verification of the proposed soft-switching PFC converter have been given. A 2 kW, 200 kHz, soft-switching PFC converter has been constructed. An efficiency of 94% at rated output power has been measured. Experimental results show the proposed digital control scheme can achieve a very high efficiency for power factor correction.

 
   Improvement of Single-Phase Power Factor Correction Circuits Using Sample-and-Hold Techniques 
 By Ninkoviæ P., Janda Ž. 
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Abstract: This paper describes improvement of single-phase PFC circuits made by using sample and hold technique in order to achieve minimum low harmonic content of the input current. Theoretical foundations are described and used to achieve a successful implementation. Guidelines for designing the regulator are presented. Experimental converter is built and tested. The results show that almost ideal THD is achieved (with high frequency content ignored) using novel technique with extremely high bandwidth.