EPE Association: EPE 2021 - System Integration

EPE 2021 - System Integration
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2021 ECCE Europe - Conference > EPE 2021 - Topic 01: Devices, Packaging and System Integration > EPE 2021 - System Integration

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   A Fast Short-Circuit Detection and Protection Method for Wide Band-gap Devices based on Current Derivative Sensing
By Johan LE LESLE [View]
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Abstract: Over the years, robust Short-Circuit (SC) detection and protection methods have been developed for silicon (Si) devices, such as Si Insulated Gate Bipolar Transistors (IGBT) or Si Metal Oxide Field Effect Transistors (MOSFET). The emergence of Wide Band-Gap (WBG) devices as Silicon Carbide (SiC) MOSFETs and Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT) brought the need of new protection methods. Indeed, the SC ruggedness of WBG devices is much lower than their Si counterparts. Moreover, the high switching speed of SiC and GaN devices requires special care regarding switching cell design. Indeed, reduction of parasitic inductance is a key parameter to fully take advantage of such components. However, low switching loop inductance can lead to very short transient before reaching the peak current during short-circuit (several hundred of Amps in few nano-seconds), making some usual SC detection methods inappropriate. On one hand, the most common method being the DeSat, may not be used as it stands for GaN. Indeed, the inherent delay time of these methods are inadequate. On the other hand, methods that are using direct current measurements, such as shunt, are also inappropriate due the degradation of the switching cell, being a key point with GaN devices. This paper proposes a fast analogue short-circuit detection and protection method for WBG devices, in particular GaN devices. The proposed circuit relies on current derivative sensing method. In fact, the current derivative pattern varies in case of short-circuit. The signal coming from the current derivative sensors is used to trigger the protection circuit placed as close as possible to the power device, shortening the protection delay time.

   A PCB based package with thermal resistance improvement
By Rémi PERRIN [View]
[Download]

Abstract: This paper describes an improvement technique of the interconnection between a die and top and bottom copper layer in a PCB. By multiplying laser drilling steps, the amount of copper in the interconnection is increased, as well as the heat transfer performances. Therefore, it makes this technique suitable for high power applications. For a fair comparison, various copper densities are proposed and analyzed. Thermal measurements are carried out to benchmark the different solutions and a comparison with analytical calculations is performed to corroborate and define the sensitivity of various parameters for further improvements.

   Investigation of 3D printed polymer-based heat dissipator for GaN transistors
By Tony GERGES [View]
[Download]

Abstract: GaN transistors are limited in their operational capabilities due to some limitations, of whichthe thermal management aspects. Until now, most of the existing heat-dissipator systems usingadditive manufacturing (AM) are based on a metallic nned heat sink, which is heavy and hasa relatively high thermal resistance. Heat dissipation based on a phase change as operated inheat pipes is more e cient. Such heat sinks have been experimented with metals or ceramicsand not by now with polymers. However, this may be of great interest. The use of polymermay enable reducing weight and cost of the thermal device. It may allow also improving thechemical compatibility of the heat pipe material and uid, as this is often a severe issue. Thiswork presents a characterization of a 3D-printed polymer-based heat pipe evaporator intendedfor GaN transistors. The electronic copper circuit on the polymer surface is created usingplastronics technology. The metallized circuit presents an adequate electrical conductivity. Thethermal characterization performed with the HFE 7000 uid, shows that it is actually possible tocover the entire heated polymer wall with active nucleation sites once the full developed nucleateboiling regime is reached. The heat conduction through the insulating polymer wall appears asthe limiting phenomenon for heat transfer.

   Study on the Optimization of the Common Source Inductance for GaN Transistors
By Xiaomeng GENG [View]
[Download]

Abstract: Optimization of the common source inductance of GaN-based transistors is investigated in this paper concerning different design levels, namely bond wires, package layout and PCB layout. The impact of different parameters is studied using 3D FEM field simulation. The simulation method is verified with experimental results. The contributions of bond wires, packaging and PCB layout in a half-bridge circuit to the common source inductance are separated, and a design guideline and a new chip layout are proposed to minimize the common source inductance. Final simulations show that the new chip layout is beneficial to reduce the common source induct-ance.

EPE 2021 - System Integration
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2021 ECCE Europe - Conference > EPE 2021 - Topic 01: Devices, Packaging and System Integration > EPE 2021 - System Integration
	[return to parent folder]

	A Fast Short-Circuit Detection and Protection Method for Wide Band-gap Devices based on Current Derivative Sensing By Johan LE LESLE	[View] [Download]
Abstract: Over the years, robust Short-Circuit (SC) detection and protection methods have been developed for silicon (Si) devices, such as Si Insulated Gate Bipolar Transistors (IGBT) or Si Metal Oxide Field Effect Transistors (MOSFET). The emergence of Wide Band-Gap (WBG) devices as Silicon Carbide (SiC) MOSFETs and Gallium Nitride (GaN) High Electron Mobility Transistors (HEMT) brought the need of new protection methods. Indeed, the SC ruggedness of WBG devices is much lower than their Si counterparts. Moreover, the high switching speed of SiC and GaN devices requires special care regarding switching cell design. Indeed, reduction of parasitic inductance is a key parameter to fully take advantage of such components. However, low switching loop inductance can lead to very short transient before reaching the peak current during short-circuit (several hundred of Amps in few nano-seconds), making some usual SC detection methods inappropriate. On one hand, the most common method being the DeSat, may not be used as it stands for GaN. Indeed, the inherent delay time of these methods are inadequate. On the other hand, methods that are using direct current measurements, such as shunt, are also inappropriate due the degradation of the switching cell, being a key point with GaN devices. This paper proposes a fast analogue short-circuit detection and protection method for WBG devices, in particular GaN devices. The proposed circuit relies on current derivative sensing method. In fact, the current derivative pattern varies in case of short-circuit. The signal coming from the current derivative sensors is used to trigger the protection circuit placed as close as possible to the power device, shortening the protection delay time.

	A PCB based package with thermal resistance improvement By Rémi PERRIN	[View] [Download]
Abstract: This paper describes an improvement technique of the interconnection between a die and top and bottom copper layer in a PCB. By multiplying laser drilling steps, the amount of copper in the interconnection is increased, as well as the heat transfer performances. Therefore, it makes this technique suitable for high power applications. For a fair comparison, various copper densities are proposed and analyzed. Thermal measurements are carried out to benchmark the different solutions and a comparison with analytical calculations is performed to corroborate and define the sensitivity of various parameters for further improvements.

	Investigation of 3D printed polymer-based heat dissipator for GaN transistors By Tony GERGES	[View] [Download]
Abstract: GaN transistors are limited in their operational capabilities due to some limitations, of whichthe thermal management aspects. Until now, most of the existing heat-dissipator systems usingadditive manufacturing (AM) are based on a metallic nned heat sink, which is heavy and hasa relatively high thermal resistance. Heat dissipation based on a phase change as operated inheat pipes is more e cient. Such heat sinks have been experimented with metals or ceramicsand not by now with polymers. However, this may be of great interest. The use of polymermay enable reducing weight and cost of the thermal device. It may allow also improving thechemical compatibility of the heat pipe material and uid, as this is often a severe issue. Thiswork presents a characterization of a 3D-printed polymer-based heat pipe evaporator intendedfor GaN transistors. The electronic copper circuit on the polymer surface is created usingplastronics technology. The metallized circuit presents an adequate electrical conductivity. Thethermal characterization performed with the HFE 7000 uid, shows that it is actually possible tocover the entire heated polymer wall with active nucleation sites once the full developed nucleateboiling regime is reached. The heat conduction through the insulating polymer wall appears asthe limiting phenomenon for heat transfer.

	Study on the Optimization of the Common Source Inductance for GaN Transistors By Xiaomeng GENG	[View] [Download]
Abstract: Optimization of the common source inductance of GaN-based transistors is investigated in this paper concerning different design levels, namely bond wires, package layout and PCB layout. The impact of different parameters is studied using 3D FEM field simulation. The simulation method is verified with experimental results. The contributions of bond wires, packaging and PCB layout in a half-bridge circuit to the common source inductance are separated, and a design guideline and a new chip layout are proposed to minimize the common source inductance. Final simulations show that the new chip layout is beneficial to reduce the common source induct-ance.