EPE Association: EPE 2020 - DS3j-1: DC Grids, Hybrid DC Circuit breakers, Real-Time Simulation and Mock-ups

EPE 2020 - DS3j-1: DC Grids, Hybrid DC Circuit breakers, Real-Time Simulation and Mock-ups
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2020 ECCE Europe - Conference > EPE 2020 - Topic 06: Grids, Smart Grids, AC & DC > EPE 2020 - DS3j-1: DC Grids, Hybrid DC Circuit breakers, Real-Time Simulation and Mock-ups

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   A current-modulus derivative-based protection method in a flexible DC grid
By JIANQUAN LIAO [View]
[Download]

Abstract: This study develops a rapid protection method for flexible DC grids. Based on the principle of modulus decomposition, common-mode (CM) and differential-mode (DM) circuits of MMC, DC transmission line, and fault transition resistance under different faults are derived, and the synthesized equivalent circuit of DC grids are finally obtained. The method utilizes a single-end derivative of CM and DM currents to construct a protection phase plane that divides different DC fault types into different regions. The proposed method is verified by simulation and experiment. This method can identify and detect faults within 1ms, which can significantly reduce the breaking current of the DC circuit breaker (DCCB).

   A Fast and Robust Model of Dual-Active Bridge Converters in Real-Time Simulation
By Ming JIA [View]
[Download]

Abstract: Real-time simulation is becoming an emerging and powerful tool for the development of power electronics conversion systems. One widely employed methods used in real-time (RT) simulations is the time average method. In this paper, a C-code average model is proposed for a two-level three-phase dualactive bridge dc-dc converter (2L-DAB3) to perform an efficient RT simulation. The calculation speed and accuracy as well as its stability with different integration methods are investigated and compared with state-of-the-art auto-generated models.

   Design, modelling, and test of a solid-state main breaker for hybrid DC circuit breaker
By Jiawen XI [View]
[Download]

Abstract: Driven by the requirements of reducing air pollutant gas emissions and fuel consumption, the concepts of more electric ship and electric aircraft are attracting increasing attention. Medium voltage DC (MVDC) distribution architectures have been proposed as potential candidates to transmit and distribute energy from generators to motors in these applications. However, the low impedance in MVDC systems results in extremely fast propagation speed of fault currents. Therefore, it is necessary to interrupt the DC fault in a very short period. This paper investigates a solid-state circuit breaker with an ultrafast interruption speed as a main breaker for a hybrid DC circuit breaker. A simulation model of the hybrid circuit breaker is established using PLECS software to evaluate the performance of the main breaker. A 1 kV solid-state main breaker prototype based on series and parallel connected insulated gate bipolar transistors (IGBTs) is built. Series and parallel connection of IGBTs are implemented to increase the voltage and current level. The maximum voltage across the solid-state circuit breaker is limited to 1.8 kV after current interruption. The solid-state main breaker prototype is experimentally tested under dynamic current conditions. The solid-state main breaker prototype successfully interrupts current of 400 A within 300 microseconds and presents good voltage balancing as well as current sharing performance. The experimental results show good agreement with the simulation results.

   Modular Hybrid DC Breaker-based Adaptive Auto-Reclosing Method for MMC-HVDC Systems
By Hossein IMANEINI [View]
[Download]

Abstract: In this paper, the modular hybrid DC breaker is employed to inject active pulses after fault-current interruption and arc extinction due to a pole-to-pole fault in MMC-HVDC systems with half-bridge submodules. The power electronic branch of hybrid DC breaker is made of n series modules, which allows generating active pulses with a controllable amplitude and pulse width. Each module is a combination of metal oxide varistor (MOV) and parallel IGBTs, which can be bypassed by the IGBTs turn-on. In the proposed method, when the fault current is interrupted and the arc is extinguished, a specific number of modules are bypassed and by this action the operating point of remaining MOVs is pushed from high resistance to temporary overvoltage (or switching surge) mode. At the new operating point, the behavior of MOVs is equivalent to a DC voltage source in series with a low resistance and the voltage difference of MMC DC-link and the equivalent DC source is applied to the line. After a short delay (equal to the desired pulse width), the breaker modules are switched off and the pulse generation is ended. This action is repeated for several times and based on the monitored waveforms on the DC line, the fault type and its characteristics are recognized. In case of temporary fault, the voltage of DC line is gradually increased by sequentially turning the breaker modules on. Finally, the validity of proposed method is verified by simulations and experiments on a scaled down prototype.

   Power Hardware in the Loop System based on Interleaved Converter and FPGA - Application to DC and AC side Emulation for Photovoltaic Inverter Testing
By Riad KADRI [View]
[Download]

Abstract: In this paper, the development of a high bandwidth power amplifier for power hardware-in-the-loop system is proposed. This amplifier consists of a multilevel interleaved converter, controlled by a real time model of a studied system that is implemented in a field programmable gate array. The accuracy of the proposed topology is illustrated with the design of a test bench for PV inverter testing. This topology is able to emulate both sides (AC and DC) of PV inverter. With this scheme it is possible to analyze the behavior of the complete photovoltaic system under special conditions like partial shading and disturbed grid voltage. The simulation and experimental results verify that the proposed topology exhibits good performance compared with classical topology.

EPE 2020 - DS3j-1: DC Grids, Hybrid DC Circuit breakers, Real-Time Simulation and Mock-ups
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2020 ECCE Europe - Conference > EPE 2020 - Topic 06: Grids, Smart Grids, AC & DC > EPE 2020 - DS3j-1: DC Grids, Hybrid DC Circuit breakers, Real-Time Simulation and Mock-ups
	[return to parent folder]

	A current-modulus derivative-based protection method in a flexible DC grid By JIANQUAN LIAO	[View] [Download]
Abstract: This study develops a rapid protection method for flexible DC grids. Based on the principle of modulus decomposition, common-mode (CM) and differential-mode (DM) circuits of MMC, DC transmission line, and fault transition resistance under different faults are derived, and the synthesized equivalent circuit of DC grids are finally obtained. The method utilizes a single-end derivative of CM and DM currents to construct a protection phase plane that divides different DC fault types into different regions. The proposed method is verified by simulation and experiment. This method can identify and detect faults within 1ms, which can significantly reduce the breaking current of the DC circuit breaker (DCCB).

	A Fast and Robust Model of Dual-Active Bridge Converters in Real-Time Simulation By Ming JIA	[View] [Download]
Abstract: Real-time simulation is becoming an emerging and powerful tool for the development of power electronics conversion systems. One widely employed methods used in real-time (RT) simulations is the time average method. In this paper, a C-code average model is proposed for a two-level three-phase dualactive bridge dc-dc converter (2L-DAB3) to perform an efficient RT simulation. The calculation speed and accuracy as well as its stability with different integration methods are investigated and compared with state-of-the-art auto-generated models.

	Design, modelling, and test of a solid-state main breaker for hybrid DC circuit breaker By Jiawen XI	[View] [Download]
Abstract: Driven by the requirements of reducing air pollutant gas emissions and fuel consumption, the concepts of more electric ship and electric aircraft are attracting increasing attention. Medium voltage DC (MVDC) distribution architectures have been proposed as potential candidates to transmit and distribute energy from generators to motors in these applications. However, the low impedance in MVDC systems results in extremely fast propagation speed of fault currents. Therefore, it is necessary to interrupt the DC fault in a very short period. This paper investigates a solid-state circuit breaker with an ultrafast interruption speed as a main breaker for a hybrid DC circuit breaker. A simulation model of the hybrid circuit breaker is established using PLECS software to evaluate the performance of the main breaker. A 1 kV solid-state main breaker prototype based on series and parallel connected insulated gate bipolar transistors (IGBTs) is built. Series and parallel connection of IGBTs are implemented to increase the voltage and current level. The maximum voltage across the solid-state circuit breaker is limited to 1.8 kV after current interruption. The solid-state main breaker prototype is experimentally tested under dynamic current conditions. The solid-state main breaker prototype successfully interrupts current of 400 A within 300 microseconds and presents good voltage balancing as well as current sharing performance. The experimental results show good agreement with the simulation results.

	Modular Hybrid DC Breaker-based Adaptive Auto-Reclosing Method for MMC-HVDC Systems By Hossein IMANEINI	[View] [Download]
Abstract: In this paper, the modular hybrid DC breaker is employed to inject active pulses after fault-current interruption and arc extinction due to a pole-to-pole fault in MMC-HVDC systems with half-bridge submodules. The power electronic branch of hybrid DC breaker is made of n series modules, which allows generating active pulses with a controllable amplitude and pulse width. Each module is a combination of metal oxide varistor (MOV) and parallel IGBTs, which can be bypassed by the IGBTs turn-on. In the proposed method, when the fault current is interrupted and the arc is extinguished, a specific number of modules are bypassed and by this action the operating point of remaining MOVs is pushed from high resistance to temporary overvoltage (or switching surge) mode. At the new operating point, the behavior of MOVs is equivalent to a DC voltage source in series with a low resistance and the voltage difference of MMC DC-link and the equivalent DC source is applied to the line. After a short delay (equal to the desired pulse width), the breaker modules are switched off and the pulse generation is ended. This action is repeated for several times and based on the monitored waveforms on the DC line, the fault type and its characteristics are recognized. In case of temporary fault, the voltage of DC line is gradually increased by sequentially turning the breaker modules on. Finally, the validity of proposed method is verified by simulations and experiments on a scaled down prototype.

	Power Hardware in the Loop System based on Interleaved Converter and FPGA - Application to DC and AC side Emulation for Photovoltaic Inverter Testing By Riad KADRI	[View] [Download]
Abstract: In this paper, the development of a high bandwidth power amplifier for power hardware-in-the-loop system is proposed. This amplifier consists of a multilevel interleaved converter, controlled by a real time model of a studied system that is implemented in a field programmable gate array. The accuracy of the proposed topology is illustrated with the design of a test bench for PV inverter testing. This topology is able to emulate both sides (AC and DC) of PV inverter. With this scheme it is possible to analyze the behavior of the complete photovoltaic system under special conditions like partial shading and disturbed grid voltage. The simulation and experimental results verify that the proposed topology exhibits good performance compared with classical topology.