EPE Association: EPE 2011 - DS2g: Topic 05: Emerging Topologies, Failure Tolerant Systems or Converters

EPE 2011 - DS2g: Topic 05: Emerging Topologies, Failure Tolerant Systems or Converters
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2011 ECCE Europe - Conference > EPE 2011 - Topic 05: Hard Switching Inverters and Control > EPE 2011 - DS2g: Topic 05: Emerging Topologies, Failure Tolerant Systems or Converters

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   A NEW FAULT DETECTION METHOD FOR NPC CONVERTERS
By Mario MARCHESONI, Paolo FAZIO, Gianmarco MARAGLIANO, Gianluca PARODI [View]
[Download]

Abstract: Neutral Point Clamped (NPC) converter topology is one of the most widespread static conversion structures used in high power medium voltage industrial applications. In recent years, fault tolerance has become one of the most interesting features which could be requested by the market, in order to improve plants reliability and availability, thus avoiding, for example, the stop of means of transport and/or plants. This paper proposes a new fault detection method for NPC converters, able to detect any type of power semiconductor device fault. The fault detection, which is very fast, is based on the measurements of load and clamp-diode legs currents and avoids the use of gate-unit feedback signals and voltage measurements across each component.

   DC-link Voltage Ripple Analysis and Impedance Network Design of Single-phase Z-source Inverter
By Yifan YU, Qianfan ZHANG, Xiaofei LIU, Shumei CUI [View]
[Download]

Abstract: One major drawback of single-phase Z-source inverter is the introduction of low-frequency DC-link voltage ripple, which does not exist in three-phase Z-source inverter. Therefore, proper sizing of impedance network of single-phase Z-source inverter becomes a serious issue. In this paper, impedance network design rules of single-phase Z-source inverter are proposed in order to limit the low-frequency DC-link voltage ripple in an acceptable range. The design rules are derived under the assumptions that open state could be considered as part of active state and linear approximation of inductor current and capacitor voltage is accurate enough. Finally, the feasibility of this impedance network design rules has been validated both by computer simulations and laboratory experiments.

   Derivation and Characterization of Switched-Boost Inverter
By Saurabh UPADHYAY, Ravindranath ADDA, Santanu MISHRA, Avinash JOSHI [View]
[Download]

Abstract: Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. This impedance network consists of two inductors and two capacitors, which causes significant increase in the size of the power converter. Moreover, for stable operation of the converter, this impedance network has to be perfectly symmetrical which is difficult to achieve in practice. In this paper, an alternative implementation of the ZSI is derived. The resulting topology is called Switched Boost Inverter (SBI). It has half the number of passive components when compared to ZSI while retaining its primary operational advantages. This paper explains the steady state operation and small signal behavior of the switched boost inverter. A laboratory prototype is used to validate the theoretical analysis. Experimental results show good correlation between theory and experiments.

   MODULAR QUASI-8-LEVEL INVERTER TOPOLOGY BY BINARY VOLTAGE ADDING THROUGH TRANSFORMERS WITH TEST BENCH RESULTS
By Helmut WEISS [View]
[Download]

Abstract: Standard multilevel inverters offer high quality output voltages at small voltage steps even without using additional filter equipment. Voltages of separate converter stages can be added by series connection of transformers. However, the number of individual switches to be controlled precisely and at given sequence is a heavy burden for control. The hardware expenditure of standard circuits is rather high, too. This proposal employs an inverter system composed of 4 identical standard 2-level inverter modules producing binary weighted voltages being added at output side windings of transformer. Eight levels of output voltage (for e.g. positive polarity, including zero) can be generated. This quasi-8-level inverter achieves high quality output voltage at low harmonics and small voltage steps at significantly lower expenditure in hardware and control set complexity than comparable standard multi-level inverters. All modules are operated at same power dissipation. Hardware is realized by modules enabling fault handling by one spare part out of four power components used (PWM circuit, transformer) for full power rating, or at power reduction by 50 \% through rearranging one module and setting aside the defective part. In order to generate the high quality output voltage a special yet simple pulse control set is introduced. This paper describes its analog and digital realization.

   Multilevel two quadrant DC/DC converter for regenerative braking in mobile applications
By Miquel MASSOT-CAMPOS, Daniel MONTESINOS-MIRACLE, Samuel GALCERAN-ARELLANO, Alfred RUFER [View]
[Download]

Abstract: In this paper different cascaded and multilevel topologies are compared for regenerative brakingsystems using supercapacitors (SC). It shows that the multilevel buck derived topology can beneficiatefrom both reduced voltage across the inductor and increased frequency to reduce the outputinductance, even if there is the need for an input LC filter to reduce harmonic content in the SC. Also,the proposed control scheme is able to control the energy flow between SC and the DC bus, balancingthe voltage in the SC banks. Experimental results verify the performance of the proposed converterand its control algorism.

   Operation of multi-phase converters with coupled inductors at reduced number of phases
By Sebastian UTZ, Johannes PFORR [View]
[Download]

Abstract: In this paper multi-phase converters with coupled inductors are analyzed when operated with reduced number of phases. An n-phase magnetic equivalent circuit model is used to show the influence of the total output current on the additional leakage inductance caused by the reduced number of phases. The analysis shows that the output current ripple is significantly reduced at light load conditions leading to reduced power losses in the converter. A converter operation with reduced number of phases can be realized and hence a fault tolerant system with coupled inductors can be achieved. FEM simulations are used to visualize the flux density in the core and to verify the theoretical predictions. A full size prototype converter with coupled inductors has been built and tested to show the converter operation with reduced number of phases. Measurements confirm the theoretical predictions very well.

   Short Fail-Safe Capability and Fault Diagnosis Strategies Dedicated to a Reconfigurable 5-Level Double-Boost PFC
By Thi Thuy Linh PHAM, Frédéric RICHARDEAU, Guillaume GATEAU [View]
[Download]

Abstract: A new 5-level reconfigurable PFC topology with low energy short-failure capability and fast fault-diagnosis is proposed. It includes a 2-stacked low energy 3-level Fly-Cap Boost through two input low frequency rectifiers. 600V-30kHz devices in series pear stack allow one short-fault for transistor and up to two short-faults for diodes. Firstly, authors shows for the first time the low ageing drift and the great stability of the parasite short-failure resistance (Rsc) of failed CoolMos™ transistors and SiC diodes inside well known epoxy molded package (TO220/TO247/TO3P cases). Secondly, two fault-diagnosis strategies are presented : one directly monitors the voltages across the flying capacitors to detect and to localize the faulty switch by means of two sensors ; other is based on a harmonic detection (magnitude and phase-shift) at the switching frequency through only one voltage sensor at the input of the PFC. All these strategies are analyzed and simulated with the efficient PD-PWM technique that exhibits a lower THD of the leg-leg input voltage for three-phase application. The design and the most important features are highlighted thanks to a digital control frame and a single-phase mock-up rated to AC115V – DC400V - 4kW – 4x31kHz.

   Single-phase Boost-type Rectifier With Fault-Tolerant Capability
By Jean-Claude LE CLAIRE, Karim CHALAL, Sony TRIESTE [View]
[Download]

Abstract: Here a recent single-phase AC/DC rectifier is analysed then proposed for building a new fault-tolerant converter. It operates in continuous current and PFC modes and it is under control of analog AC and DC controllers. This Boost-type rectifier involves two switches and can operate in different ways thus improves the continuity of the energy transfer in case of failures.

   Solutions of DC-DC converters for G-class audio amplifiers in mobile platforms
By Xavier BRANCA, Bruno ALLARD, Xuefang LIN-SHI [View]
[Download]

Abstract: This paper presents a study and an analysis of the existing solutions for driving headphones in mobile platforms. solution converge to the use of G class audio amplifier. Such an amplifier requires a symmetrical power supply in order to get rid of huge external capacitors. Voltage scaling is mandatory in order to increase the system efficiency. The system is to be integrated into a mobile platform. The paper proposes to study three architectural solutions for the supply of such amplifiers. These architectures are benchmarked and discussed. The criterion taken into account for discrimination are the price and the footprint of external passives components, the silicon area, the number of IOs and the power efficiency. A single inductor, double output DC/DC converter is identified as an original and efficient candidate for this power supply. A primary prototype of the proposed architecture has been realized in a 130 nm CMOS process. The non-optimized testchip works in PWM in CCM and achieves 80\% peak efficiency at 360 mW output power. Audio amplifiers are embedded on the same chip. The functionality of G class audio amplifiers supplied by this DC/DC converter is validated as well as the voltage scaling operation.

   Study on the PWM Methods of an Energy Storage Devices Directly Connected Inverter with EDLCs
By Yoshihiro IDE, Keiichiro KONDO [View]
[Download]

Abstract: In this paper, the unbalanced input voltage three level inverter, which is able to absorb the regenerativebrake power and to output more voltage with the electro double layer capacitor (EDLC) connected inseries, is studied. The harmonics characteristics are discussed both theoretically and experimentally.The calculated results of the theoretical harmonics are verified by the experimental tests results.

EPE 2011 - DS2g: Topic 05: Emerging Topologies, Failure Tolerant Systems or Converters
You are here: EPE Documents > 01 - EPE & EPE ECCE Conference Proceedings > EPE 2011 ECCE Europe - Conference > EPE 2011 - Topic 05: Hard Switching Inverters and Control > EPE 2011 - DS2g: Topic 05: Emerging Topologies, Failure Tolerant Systems or Converters
	[return to parent folder]

	A NEW FAULT DETECTION METHOD FOR NPC CONVERTERS By Mario MARCHESONI, Paolo FAZIO, Gianmarco MARAGLIANO, Gianluca PARODI	[View] [Download]
Abstract: Neutral Point Clamped (NPC) converter topology is one of the most widespread static conversion structures used in high power medium voltage industrial applications. In recent years, fault tolerance has become one of the most interesting features which could be requested by the market, in order to improve plants reliability and availability, thus avoiding, for example, the stop of means of transport and/or plants. This paper proposes a new fault detection method for NPC converters, able to detect any type of power semiconductor device fault. The fault detection, which is very fast, is based on the measurements of load and clamp-diode legs currents and avoids the use of gate-unit feedback signals and voltage measurements across each component.

	DC-link Voltage Ripple Analysis and Impedance Network Design of Single-phase Z-source Inverter By Yifan YU, Qianfan ZHANG, Xiaofei LIU, Shumei CUI	[View] [Download]
Abstract: One major drawback of single-phase Z-source inverter is the introduction of low-frequency DC-link voltage ripple, which does not exist in three-phase Z-source inverter. Therefore, proper sizing of impedance network of single-phase Z-source inverter becomes a serious issue. In this paper, impedance network design rules of single-phase Z-source inverter are proposed in order to limit the low-frequency DC-link voltage ripple in an acceptable range. The design rules are derived under the assumptions that open state could be considered as part of active state and linear approximation of inductor current and capacitor voltage is accurate enough. Finally, the feasibility of this impedance network design rules has been validated both by computer simulations and laboratory experiments.

	Derivation and Characterization of Switched-Boost Inverter By Saurabh UPADHYAY, Ravindranath ADDA, Santanu MISHRA, Avinash JOSHI	[View] [Download]
Abstract: Z-source inverter (ZSI) employs an LC impedance network between the main inverter bridge and the power source. This impedance network consists of two inductors and two capacitors, which causes significant increase in the size of the power converter. Moreover, for stable operation of the converter, this impedance network has to be perfectly symmetrical which is difficult to achieve in practice. In this paper, an alternative implementation of the ZSI is derived. The resulting topology is called Switched Boost Inverter (SBI). It has half the number of passive components when compared to ZSI while retaining its primary operational advantages. This paper explains the steady state operation and small signal behavior of the switched boost inverter. A laboratory prototype is used to validate the theoretical analysis. Experimental results show good correlation between theory and experiments.

	MODULAR QUASI-8-LEVEL INVERTER TOPOLOGY BY BINARY VOLTAGE ADDING THROUGH TRANSFORMERS WITH TEST BENCH RESULTS By Helmut WEISS	[View] [Download]
Abstract: Standard multilevel inverters offer high quality output voltages at small voltage steps even without using additional filter equipment. Voltages of separate converter stages can be added by series connection of transformers. However, the number of individual switches to be controlled precisely and at given sequence is a heavy burden for control. The hardware expenditure of standard circuits is rather high, too. This proposal employs an inverter system composed of 4 identical standard 2-level inverter modules producing binary weighted voltages being added at output side windings of transformer. Eight levels of output voltage (for e.g. positive polarity, including zero) can be generated. This quasi-8-level inverter achieves high quality output voltage at low harmonics and small voltage steps at significantly lower expenditure in hardware and control set complexity than comparable standard multi-level inverters. All modules are operated at same power dissipation. Hardware is realized by modules enabling fault handling by one spare part out of four power components used (PWM circuit, transformer) for full power rating, or at power reduction by 50 \% through rearranging one module and setting aside the defective part. In order to generate the high quality output voltage a special yet simple pulse control set is introduced. This paper describes its analog and digital realization.

	Multilevel two quadrant DC/DC converter for regenerative braking in mobile applications By Miquel MASSOT-CAMPOS, Daniel MONTESINOS-MIRACLE, Samuel GALCERAN-ARELLANO, Alfred RUFER	[View] [Download]
Abstract: In this paper different cascaded and multilevel topologies are compared for regenerative brakingsystems using supercapacitors (SC). It shows that the multilevel buck derived topology can beneficiatefrom both reduced voltage across the inductor and increased frequency to reduce the outputinductance, even if there is the need for an input LC filter to reduce harmonic content in the SC. Also,the proposed control scheme is able to control the energy flow between SC and the DC bus, balancingthe voltage in the SC banks. Experimental results verify the performance of the proposed converterand its control algorism.

	Operation of multi-phase converters with coupled inductors at reduced number of phases By Sebastian UTZ, Johannes PFORR	[View] [Download]
Abstract: In this paper multi-phase converters with coupled inductors are analyzed when operated with reduced number of phases. An n-phase magnetic equivalent circuit model is used to show the influence of the total output current on the additional leakage inductance caused by the reduced number of phases. The analysis shows that the output current ripple is significantly reduced at light load conditions leading to reduced power losses in the converter. A converter operation with reduced number of phases can be realized and hence a fault tolerant system with coupled inductors can be achieved. FEM simulations are used to visualize the flux density in the core and to verify the theoretical predictions. A full size prototype converter with coupled inductors has been built and tested to show the converter operation with reduced number of phases. Measurements confirm the theoretical predictions very well.

	Short Fail-Safe Capability and Fault Diagnosis Strategies Dedicated to a Reconfigurable 5-Level Double-Boost PFC By Thi Thuy Linh PHAM, Frédéric RICHARDEAU, Guillaume GATEAU	[View] [Download]
Abstract: A new 5-level reconfigurable PFC topology with low energy short-failure capability and fast fault-diagnosis is proposed. It includes a 2-stacked low energy 3-level Fly-Cap Boost through two input low frequency rectifiers. 600V-30kHz devices in series pear stack allow one short-fault for transistor and up to two short-faults for diodes. Firstly, authors shows for the first time the low ageing drift and the great stability of the parasite short-failure resistance (Rsc) of failed CoolMos™ transistors and SiC diodes inside well known epoxy molded package (TO220/TO247/TO3P cases). Secondly, two fault-diagnosis strategies are presented : one directly monitors the voltages across the flying capacitors to detect and to localize the faulty switch by means of two sensors ; other is based on a harmonic detection (magnitude and phase-shift) at the switching frequency through only one voltage sensor at the input of the PFC. All these strategies are analyzed and simulated with the efficient PD-PWM technique that exhibits a lower THD of the leg-leg input voltage for three-phase application. The design and the most important features are highlighted thanks to a digital control frame and a single-phase mock-up rated to AC115V – DC400V - 4kW – 4x31kHz.

	Single-phase Boost-type Rectifier With Fault-Tolerant Capability By Jean-Claude LE CLAIRE, Karim CHALAL, Sony TRIESTE	[View] [Download]
Abstract: Here a recent single-phase AC/DC rectifier is analysed then proposed for building a new fault-tolerant converter. It operates in continuous current and PFC modes and it is under control of analog AC and DC controllers. This Boost-type rectifier involves two switches and can operate in different ways thus improves the continuity of the energy transfer in case of failures.

	Solutions of DC-DC converters for G-class audio amplifiers in mobile platforms By Xavier BRANCA, Bruno ALLARD, Xuefang LIN-SHI	[View] [Download]
Abstract: This paper presents a study and an analysis of the existing solutions for driving headphones in mobile platforms. solution converge to the use of G class audio amplifier. Such an amplifier requires a symmetrical power supply in order to get rid of huge external capacitors. Voltage scaling is mandatory in order to increase the system efficiency. The system is to be integrated into a mobile platform. The paper proposes to study three architectural solutions for the supply of such amplifiers. These architectures are benchmarked and discussed. The criterion taken into account for discrimination are the price and the footprint of external passives components, the silicon area, the number of IOs and the power efficiency. A single inductor, double output DC/DC converter is identified as an original and efficient candidate for this power supply. A primary prototype of the proposed architecture has been realized in a 130 nm CMOS process. The non-optimized testchip works in PWM in CCM and achieves 80\% peak efficiency at 360 mW output power. Audio amplifiers are embedded on the same chip. The functionality of G class audio amplifiers supplied by this DC/DC converter is validated as well as the voltage scaling operation.

	Study on the PWM Methods of an Energy Storage Devices Directly Connected Inverter with EDLCs By Yoshihiro IDE, Keiichiro KONDO	[View] [Download]
Abstract: In this paper, the unbalanced input voltage three level inverter, which is able to absorb the regenerativebrake power and to output more voltage with the electro double layer capacitor (EDLC) connected inseries, is studied. The harmonics characteristics are discussed both theoretically and experimentally.The calculated results of the theoretical harmonics are verified by the experimental tests results.