| Abstract |
The paper demonstrates how a simple, low-cost and effective stator resistance estimation scheme for FPGA can be employed, utilizing the large degree of freedom a FPGA impose with regard to system design, while at the same time conform to the constraints the same technology infer. In a computing system, a FPGA removes the limitations of the Von Neuman-architecture. Although the (Super) Harward architecture, used by most DSP processors, relieve this limitations, this is not anywhere near the power of the parallel computing capability of FPGA. A FPGA is at the same time somewhat limited with regard to complexity of mathematical operations. Although this limitations has been removed with the introduction of FPGA with embedded CPU, there are still reasons for keeping the design simple, when overall cost should kept low. The estimator has been tested on an asynchronous machine, with satisfying results. |
