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Digital compensation of a high-frequency voltage-mode dc-dc converter
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| Author(s) |
CHANG Wei-Hsu; HSIA Tsun-Hsiao; LIN Yu-Zheng; CHEN Dan; TSAI Hsien-Yi |
| Abstract |
This paper explores the potential and the pitfall of digital compensation in a voltage-mode dc-dc converter. A FPGA-based synchronous DC-DC buck converter was used to implement the proposed two digital compensating schemes. One was to use a pair of complex compensating zeros and the other was to use a positive pole. Small-signal models of converters with digital control will be used to illustrate some basic concepts. Complex-zero compensation may improve the control loop gain characteristics but positive-pole compensation is infeasible |
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| Filename: | 0349-epe2007-full-03254068.pdf |
| Filesize: | 473.1 KB |
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| Type |
Members Only |
| Date |
Last modified 2008-01-11 by System |
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