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Driver Chip Design Considerations for VRM Applications
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| Author(s) |
Shih-hui Chen, Chung-Lung Pai, Dan Chen, Jing-meng Liu, Calvin Juang |
| Abstract |
In this paper, a power loss model of VRMs will
first be given. Actual power loss distribution on VRMs will
be estimated for various VRM conditions. Comments will be
made from the observations of the results and suggestions
be made from the point of view of gate driver chip design.
Discussion of future improvement possibilities is presented. |
| Download |
| Filename: | T6-102.pdf |
| Filesize: | 768.8 KB |
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| Type |
Members Only |
| Date |
Last modified 2007-03-08 by System |
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