| Abstract |
In many Buck converter applications, soft start
feature with pre-biased output voltage condition is often
necessary to avoid undesirable effects such as in-rush start
current, possible inductor saturation, and output voltage
overshoot during power-up period. However, in a
synchronous Buck converter configuration, such starting
condition would lead to output voltage temporary dipping
during power-up, which is disallowed in many applications.
In this paper, a novel control circuit is proposed to mitigate
such a problem. Circuit-level SPICE simulations were
conducted to verify the concept. The proposed circuit
concept was experimentally verified by using discrete
components at the breadboard level. Although the
experimental verification was done with discrete
components, however, the circuit was conceived with the
intention of integrated circuit fabrication. |
