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Suggested Stabilizing Loops for Prevention of Core Saturation Instability in HVDC Systems
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| Author(s) |
I. Norheim; T. Undeland |
| Abstract |
Different stabilizing loops have been inserted into a modified CIGRE HVDC benchmark model which is more vulnerable for core saturation instability than the original CIGRE HVDC benchmark model. By using the simulation program PSCAD/EMTDC version 3 it is demonstrated that these may prevent development of core saturation instability. Of special interest it is shown how FFT functions may improve stabilizing loops. |
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| Filename: | Unnamed file |
| Filesize: | 246.7 KB |
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| Type |
Members Only |
| Date |
Last modified 2006-02-27 by System |
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