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FPGA Based Dead-Time Compensation for PWM inverters
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| Author(s) |
IKONEN Mika; LAAKKONEN Ossi; SILVENTOINEN Pertti; PYRHOeNEN Olli; RAUMA Kimmo |
| Abstract |
Dead-times of power switches causes significant errors in some electric drive applications. Compensation of the error can be done with a small amount of discrete components and small programmable logic circuit. Larger Field Programmable Gate Array (FPGA) circuit allows integration of the modulator and compensation logic in the same circuit resulting a very compact and cheap solution. This paper presents one solution to implement a dead-time compensation logic with a cheap and exact voltage feedback and a simple logic that can be implemented in a FPGA or Application Specific Integrated Circuits (ASIC). Full test system and measurement results are presented. |
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| Filename: | 0334 |
| Filesize: | 390.1 KB |
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| Type |
Members Only |
| Date |
Last modified 2006-02-05 by System |
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