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   Phase-Locked Loop for Static Series Compensator   [View] 
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 Author(s)   H. Awad; J. Svensson; M. Bollen 
 Abstract   Accurate phase information is crucial for most of the modern power electronics apparatus such as the static series compensator. A software phase-locked loop (SPLL) has been proposed in literature to obtain phase and frequency information of the grid voltage. Either a lead/lag filter or a PI-controller is employed to control the performance of the SPLL. However, it has not been declared how to tune the SPLL for SSC applications. In this paper, a criterion to tune the SPLL for SSC applications is discussed and the gains of the PI-controller are determined to obtain the desired performance. The proposed criterion is based on the fact that a phase angle jump of the grid voltage is sensed as a frequency deviation by the load, and owing to European standard, most of the loads should function properly if the deviation of the grid frequency is kept within ± 1Hz. Unbalanced grid voltages are separated into positive and negative sequences and the SPLL is locked to the positive sequence. The response of the SPLL has been evaluated by applying phase step of the actual grid phase. Also, the SSC together with the SPLL have been modeled and simulated using PSCAD/EMTDC package. Simulation results in case of a voltage dip associated with a phase jump is presented. 
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Filename:EPE2003-PP0005 - Awad.pdf
Filesize:953.2 KB
 Type   Members Only 
 Date   Last modified 2003-11-06 by System