| Abstract |
A novel digital voltage controller for boost PFC converters is presented in this paper. Some controlled
boost PFC converters emulate a resistive input impedance to the mains by forcing the line current to
track the wave shape of the mains voltage. In that way these converters exhibit a low THD of the AC
input current and maintain a high power factor. However, as an analogue voltage controller is applied to
maintain a constant DC output voltage, the DC-bus voltage ripple, pulsating at twice the grid frequency,
injects a third harmonic of considerable magnitude in the AC input current. Over the last decade, several
voltage control strategies for lowering third harmonic distortion in the line current, have been reported
in the literature. One of the output voltage control algorithms that catches the eye due to its straightforwardness
and to its intrinsic discrete-time approach, is the sample-and-hold method. The proposed
digital voltage compensator is an improvement of this method. By sampling the DC-bus voltage at all
zeroes of its ripple, the new strategy results in a fast voltage control algorithm that guarantees low total
harmonic distortion in the AC input current. The timing of the zeroes in the ripple of the DC-bus voltage
for a rated load as well as for a light load and the reduction of the ripple in the sampled DC-bus voltage
are described. The good results of a voltage compensator based on the proposed sample-and-hold
method and the improvements of such a compensator against commonly employed voltage controllers
are verified experimentally using a digitally controlled boost PFC converter. |
