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   Input preprocessing in tapped delay neural architecture for induction motor speed estimation   [View] 
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 Author(s)   L. M. Grzesiak; B. Beliczynski; B. Ufnalski 
 Abstract   Tapped delay neural architecture with input preprocessing for induction motor speed estimation is analysed. We start with a typical set of easily measurable electrical signals and demonstrate that a nonlinear input peprocessing is needed with possibly more outputs than inputs. When sufficiently many linearly independant variables are generated through that preprocessing, one may reduce number of delays in this architecture even to zero. Laboratory results are reported. 
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Filename:EPE2003-PP0863 - Grzesiak
Filesize:280.6 KB
 Type   Members Only 
 Date   Last modified 2003-10-23 by Unknown