| |
A Co-Simulation Environment For The Test And The Validation Of Digital Control Strategy On A Mixed DSP/FPGA Architecture
| [View]
[Download]
|
| Author(s) |
G. Gateau, R. Ruelland, M. Aime |
| Abstract |
The digital control in power electronics is used
very frequently and makes it possible to obtain a very high
flexibility compared to analogical solutions. Digital technology
also brings to us a good precision as well as an excellent
reliability. The severe time constraints expressed for the control
of power converters lead us logically towards an digital
architecture based on an association between a DSP and a
FPGA. The DSP in this association is dedicated to numerical
calculations, the diagnosis and also to the monitoring of the
system. The FPGA will be used for all the tasks requiring a
short treatment and latency time. The digital designer must then
be able to use his expertise to distribute the different tasks of the
control on this mixed architecture before considering the
implementation on the real system.
A new and important stage appears then in the development
of the digital control strategy, it is the simulation of the whole
digital system by taking into account the selected architecture as
well as the allocation of the tasks on the architecture. This stage
is called Co-simulation and makes it possible to simulate in the
same environment the part integrated on the FPGA and the
code carried out on the DSP. In addition, co-simulation step
makes it possible to test the interactions between the digital parts
of the control system and a simulation of the real system. Thus
we obtain the concept of virtual prototyping where the power
converter and the digital part of the control are simulated
together, each one using the finest possible representation.
Many techniques of Co-simulation exists and we chose a
technique known as multi-language which consists in
interfacing various dedicated simulators. Thus at the present
time, we use a simulator of microprocessor for the DSP part
written in C language and a VHDL simulator (ModelSim™)
which enables us to simulate the code established in the FPGA
after placement and routing on the component (integration of
the propagation times and structure of the component). We also
used the SABER™ simulator which enables us to simulate our
power electronic part.
In this article, we will present in a first part the tool of Cosimulation
developed in our laboratory made up of two main
simulators which are ModelSim™ for VHDL and SABER™ for
power electronics parts. We will describe then the development
of two applications of control of multilevel converters. The first
application will relate to the development and the integration in
a FPGA of the control of a multicell converter with different
solution for the partitioning. In the second time, we will present
the development and the integration of a control strategy in
current mode dedicated to a multilevel converter. These two
applications have used Co-simulation stage during their
development and we will present for the last application some
experimental results. |
| Download |
| Filename: | A32616 |
| Filesize: | 488.1 KB |
|
| Type |
Members Only |
| Date |
Last modified 2006-02-16 by System |
| |
 |