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Analyzing Of The Mos-Fet Turn-Off
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| Author(s) |
Oto Tezak, Drago Dolinar, Miro Milanovic |
| Abstract |
Presented is the analysis and the design of the turnoff
snubber circuits for low power dc-dc converters realized with
MOS-FETs. The appropriate usage of the snubber circuit can
increase the power range of the low-power dc-dc converters
available as integrated circuit. The evaluation of snubber circuit
is based on experimental results. The power transistor
dissipation can be 30% lower in the case that the efficiency of
converter not changes. Benefits, drawbacks and limits of the
proposed approach are detailed and studied. |
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| Filename: | A14525 |
| Filesize: | 381.6 KB |
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| Type |
Members Only |
| Date |
Last modified 2006-02-15 by System |
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