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FPGA PLL For High Power Factor And Low Harmonics Content Active Rectifier
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| Author(s) |
Henning Holmberg, Trond Ostrem, Waldemar Sulkowski |
| Abstract |
A design of a circuit for synchronizing a three-phase
pulse width modulated voltage source inverter (PWM-VSI) to
the utility grid. The inverter is used as an active four quadrant
rectifier with reactive power compensation. Today, when the
difference between software and hardware is less and less clear,
the solutions employing software phase-locked loop (PLL) in the
hardware FPGA give us a new flexible tool. The synchronizing
circuit works as a PLL based on a Field Programmable Gate
Array (FPGA). The main purpose is to achieve a robust and
reliable syncronization circuit. Another major task is to reduce
the harmonic components of the currents, due to the IEC
standards, and to maximize the power factor. |
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| Filename: | A12398 |
| Filesize: | 99.11 KB |
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| Type |
Members Only |
| Date |
Last modified 2006-02-17 by System |
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