This paper discusses the design of a digital current controller for three-phase utility-connected 2-level and 3-level PWM inverters with output LCL filters in which the filter capacitors are connected to the dc link rails. The controller has a two-loop feedback structure, with an additional feedforward loop to compensate for utility voltage harmonic disturbance. A detailed analysis of the effect of the controller microprocessor time delay on the stability and transient response of the controller is presented. Analytical and simulation results are presented for both the 2-level and the 3-level inverter systems, demonstrating the effectiveness of the proposed controller in producing good quality current with low THD. The results confirm that using a 3-level inverter has the advantage of halving the current ripple in the filter’s main inductors, at the expense of extra inverter power devices and electronic hardware and software complexity. Experimental results for a 2-level inverter system are also presented.
| Filename: | EPE Journal - 14-4 - 3 - Abu Sharkh |
| Filesize: | 156.9 KB |
